AR# 40089


Design Assistant for XST - Help with Register Balancing


Please refer to this answer record for help with Register Balancing.

Note: This Answer Record is a part of the Xilinx Solution Center for XST (Xilinx Answer 38927). The Xilinx Solution Center for XST is available to address all questions related to XST. Whether you are starting a new design or troubleshooting a problem, use the Solution Center for XST to guide you to the right information.


Register Balancing is an XST option/constraint which enables flip-flop retiming algorithm in Synthesis process. The main goal of Register Balancing is to improve design timing performance in the way of moving flip-flops and latches across logic to increase clock frequency.

Register Balancing has two categories:

  • Forward Register Balancing: move a set of flip-flops that are at the inputs of a LUT to a single flip-flop at its output
  • Backward Register Balancing: move a flip-flop which is at the output of a LUT to a set of flip-flops at its inputs

You can apply Register Balancing constraint globally or to a specific entity, module, signal, flip-flop or clock signal. Refer to Xilinx Answer 39749 for help with applying XST constraints.

Some considerations when using Register Balancing:

  • Register Balancing option is disabled by default because it leads to significant design structure changes.
  • The number of flip-flops in the design can be increased or decreased.
  • Register Balancing may happen across cross-clock domain boundaries. Make sure the cross-clock domain timing paths are constrained in the design.
  • The following constraints influence Register Balancing:
    • Keep Hierarchy: Hierarchy preservation limits FF movements inside the block boundaries
    • KEEP: Keep constraint applied to signals does not allow FFs to cross these signals
    • IOB: Register Balancing will be not applied to the FFs having property "IOB=true"

For more information of Register Balancing, please refer to XST User Guide See (Xilinx Answer 38931).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
38927 Xilinx Solution Center for XST N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40085 Design Assistant for XST - Performance Considerations N/A N/A
AR# 40089
Date 12/15/2012
Status Active
Type General Article
People Also Viewed