Register Balancing is an XST option/constraint which enables flip-flop retiming algorithm in Synthesis process. The main goal of Register Balancing is to improve design timing performance in the way of moving flip-flops and latches across logic to increase clock frequency.
Register Balancing has two categories:
You can apply Register Balancing constraint globally or to a specific entity, module, signal, flip-flop or clock signal. Refer to Xilinx Answer 39749 for help with applying XST constraints.
Some considerations when using Register Balancing:
For more information of Register Balancing, please refer to XST User Guide See (Xilinx Answer 38931).
Answer Number | Answer Title | Version Found | Version Resolved |
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38927 | Xilinx Solution Center for XST | N/A | N/A |
Answer Number | Answer Title | Version Found | Version Resolved |
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40085 | Design Assistant for XST - Performance Considerations | N/A | N/A |
AR# 40089 | |
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Date | 12/15/2012 |
Status | Active |
Type | General Article |