AR# 40089

Description

Solution

Register Balancing is an XST option/constraint which enables flip-flop retiming algorithm in Synthesis process. The main goal of Register Balancing is to improve design timing performance in the way of moving flip-flops and latches across logic to increase clock frequency.

Register Balancing has two categories:

• Forward Register Balancing: move a set of flip-flops that are at the inputs of a LUT to a single flip-flop at its output
• Backward Register Balancing: move a flip-flop which is at the output of a LUT to a set of flip-flops at its inputs

You can apply Register Balancing constraint globally or to a specific entity, module, signal, flip-flop or clock signal. Refer to Xilinx Answer 39749 for help with applying XST constraints.

Some considerations when using Register Balancing:

• Register Balancing option is disabled by default because it leads to significant design structure changes.
• The number of flip-flops in the design can be increased or decreased.
• Register Balancing may happen across cross-clock domain boundaries. Make sure the cross-clock domain timing paths are constrained in the design.
• The following constraints influence Register Balancing:
  • Keep Hierarchy: Hierarchy preservation limits FF movements inside the block boundaries
  • KEEP: Keep constraint applied to signals does not allow FFs to cross these signals
  • IOB: Register Balancing will be not applied to the FFs having property "IOB=true"

For more information of Register Balancing, please refer to XST User Guide See (Xilinx Answer 38931).

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