Description

Solution

There are registers in the IOB or IOLOGIC structures. The input register (register connected to the input pad) and output register (register connected to the output pad) can be packed into IOB or IOLOGIC. The IOB registers have the minimal routing delay to the I/O pads and provide fixed setup and clock-to-out times. So, using IOB register helps to improve the input/output timing performance. However, it may negatively affect the internal timing because the routing delays to internal logic can be lengthened.

The IOB constraint of XST controls the IOB register usage in Synthesis process. The default value of IOB constraint is auto, which means XST takes into account timing constraints and automatically decides to push or not to pushregisters into IOBs.It can beapplied globally or specifically to an entity, module or register. For help applying XST constraints, please refer to Xilinx Answer39749.

There are some restrictionswhich prevent registers from being packed into IOB/IOLOGIC:

• The register must be connected to an I/O buffer to be eligible for the I/O component pack. Output flip-flops should drive only the output buffer since there is no resource to allow the register to drive back out into the fabric.
• The register's control signals must be compatible with the control signals of other registers in the I/O component.
• If the I/O register is in a different hierarchy than the rest of the I/O logic, the I/O register pack can be blocked by KEEP HIERARCHY constraints.
• A KEEP net constraint on the net between the I/O register and I/O buffer can prevent the I/O component pack.

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