Description

Solution

This error message comes when there is a mismatch between name of formal ports used in component/module definition and the ones used while
instantiating them.

What is formal port ?

A formal port is a port that is declared in the module/component/entity header and used in the body of the module/component/entity. See the EXAMPLE for more elaboration.

WHAT NEXT:
Use correct formal port name while instantiating module/component or entity.

EXAMPLE:

Consider the following RTL:

library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity top is
port (vhdlinport : in std_logic;
vhdloutport : out std_logic);
end top;
architecture arch_IncrBindMixedAssoc04_top of top is
component low is
port (comp_veriloginport : in std_logic;
comp_verilogoutport : out std_logic);
end component;

begin
U1 : low
port map (vhdlinport, comp_verilogoutport => vhdloutport);
end ;
configuration config_IncrBindMixedAssoc04_top of top is
for arch_IncrBindMixedAssoc04_top
for U1 : low
port map (comp_veriloginport, verilogoutport => comp_verilogoutport);
end for;
end for;
end config_IncrBindMixedAssoc04_top;

`timescale 1ns/1ns
module low (veriloginport, verilogoutport) ;
input veriloginport ;
output verilogoutport ;
assign verilogoutport = veriloginport;
endmodule

In this example, the formal port declared in the module 'low' are 'veriloginport' and 'verilogoutport'. While the instantiation in the architecture 'arch_IncrBindMixedAssoc04_top', port map uses a port name 'comp_verilogoutport' which is not present in the module 'low'.Using the correct formal port name, i.e. 'verilogoutport' should fix the problem.

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