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AR# 40191

7 Series - LVDS compatibility between 1.8V LVDS and 2.5V LVDS signals


7 Series FPGAs require 1.8V for the VCCO level for High Performance (HP) I/O banks with LVDS outputs. 

Are there compatibility issues with LVDS compliant drivers or receivers?   


There should be no compatibility issues with the 7 series LVDS and LVDS_25 inputs and outputs, when interfacing with LVDS-compliant drivers and receivers.  

The TIA/EIA-644 LVDS standard specifies the minimum and maximum differential and common-mode voltages for LVDS compatible inputs and outputs for compliant devices.  


The 7 series data sheets indicate the electrical specifications for the Xilinx 7 series LVDS (HP banks) and LVDS_25 (HR banks) inputs and outputs.

There are no cases where any of the output specifications would violate a TIA/EIA-644 compliant receiver, or the input specifications would violate a TIA/EIA-644 compliant driver.  


If, for any reason, another device is not compliant with standard LVDS (TIA/EIA-644), the designer may be able to alter/modify the board termination schemes to obtain compliance to the driver and receiver specifications. 


When interfacing using LVDS in the High Performance bank, you can refer to this checklist to ensure that the signaling will work. 



Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47900 SelectIO Design Assistant: Interfacing to Xilinx devices N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
41408 7 Series - How to place LVDS in a High Performance bank N/A N/A
AR# 40191
Date 10/14/2014
Status Active
Type General Article
Devices More Less
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