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  1. Xilinx - All Programmable
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  3. AR# 40206: 13.1 EDK, AXI_FIFO_MM_S - "ERROR:PhysDesignRules - Issue with pin connections and/or configuration on block RAMB18E1_RAMB18E1"

AR# 40206

13.1 EDK, AXI_FIFO_MM_S - "ERROR:PhysDesignRules - Issue with pin connections and/or configuration on block RAMB18E1_RAMB18E1"

Description

When I use theAXI_FIFO_MM_S core in EDK 13.1 in a 7-Series device, the following error occurs:

"ERROR:PhysDesignRules - Issue with pin connections and/or configuration on block:<COMP_IPIC2AXI_S/COMP_RX_FIFO/COMP_BRAM/RAMB16>:<RAMB18E1_RAMB18E1>. For SDP mode, WRITE_WIDTH_A should be set to the maximum value of 18 to achieve proper block operation"

How do I resolve it?

Solution

This issue is planned to be fixed in EDK 13.2.
AR# 40206
Date 05/19/2012
Status Active
Type Error Message
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
Tools
  • EDK - 13.1
IP
  • AXI Streaming FIFO