Description

It is not clear from the Spartan-6 FPGA SelectIO Resources User Guide (UG381) how long the BITSLIP should be asserted.

What are the requirements for BITSLIP?

Solution

The BITSLIP has to be synchronous to CLKDIV, and it is recommended that it is asserted High for only 1 CLKDIV cycle.

BITSLIP can be held high for consecutive cycles of CLKDIV,which will result in multiple Bitslip operations.

Due to the latency through the ISERDES, in practice you would not issue multiple Bitslips as you would need to monitor the ISERDES output after each Bitslip operation to check if the training pattern has being found.

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