The following are the changes requiredfor the UCF:
Virtex-6 FPGA UCF changes:
UCF constraints generated by MIG:
INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/genblk*.gen_ck_cpt[0].u_oserdes_cpt" LOC = "OLOGIC_X1Y301";
INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/genblk*.gen_ck_cpt[0].u_odelay_cpt"LOC = "IODELAY_X1Y301";
Changed UCF constraint to makeassignments compatible withSynplifyE-2010.09-1-SP2:
INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt"LOC = "OLOGIC_X1Y301";
INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_odelay_cpt"LOC = "IODELAY_X1Y301";
Spartan-6 FPGA UCF changes:
UCF constraints generated by MIG:
NET
"memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/genblk*.gen_term_calib.mcb_soft_calibration_top_inst/
mcb_soft_calibration_inst/cke_train" TIG; ## This path exists for DDR2 only
Changed UCF constraint to makeassignments compatible withSynplifyE-2010.09-1-SP2:
NET
"memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/
mcb_soft_calibration_inst/cke_train" TIG; ## This path exists for DDR2 only
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
39128 | MIG Virtex-6 and Spartan-6 v3.7 - Release Notes and Known Issues for ISE Design Suite 13.1 | N/A | N/A |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
39128 | MIG Virtex-6 and Spartan-6 v3.7 - Release Notes and Known Issues for ISE Design Suite 13.1 | N/A | N/A |