AR# 40314

Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v2.1 (AXI) - 1000BASE-X functional simulation does not complete

Description

When 1000BASE-X or SGMII is selected and the PHY loopback enabled, additional waits need to be added to the testbench to ensure that the GTX has locked before data is sent. In this configuration, the transceiver drops sync after loopback is turned off. The demo_tb correctly waits to avoid corrupting data on the power on reset, but does not wait for the later resets. The demo_tb needs to be updated to add the required delays after each reset in the test.

Solution

In the demo_tb p_management process, each call to mac_reset is followed by a wait for the serial_response (or mdio_done) to assert. In the first call to mac_reset, there is an additional delay of 20 microseconds and a check to ensure the syncacqstatus output is asserted. This delay and check(highlighted in red) should be replicated for each call to mac_reset. i.e.,:

VHDL:
mac_reset;
base_x_switch_edge <= '1';
wait until gtx_clk'event and gtx_clk = '1';
base_x_switch_edge <= '0';
wait until gtx_clk'event and gtx_clk = '1';
configuration_busy <= true;

wait until serial_response = '1';
-- wait until the gtx has acquired lock
wait for 20 us;
wait until gtx_clk'event and syncacqstatus = '1';

for j in 0 to 49 loop
wait until gtx_clk'event and gtx_clk = '1';
end loop;

Verilog:
mac_reset;
base_x_switch_edge <= 1'b1;
@(posedge gtx_clk);
base_x_switch_edge <= 1'b0;
@(posedge gtx_clk);

@(posedge serial_response);
// ensure the sync has been acquired - may have already asserted so cannot just look for edge
#20000000;
while (syncacqstatus == 0) begin
@(posedge gtx_clk);
end

repeat (50) @(posedge gtx_clk);

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AR# 40314
Date	02/25/2011
Status	Active
Type	General Article
IP	Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper

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