AR# 40379: Design Assistant for XST Help understanding the XST report to resolve errors\warnings
AR# 40379
Design Assistant for XST Help understanding the XST report to resolve errors\warnings
Description
Refer to this Answer Record for help understanding the XST report to resolve errors\warnings
Note: This Answer Record is a part of the Xilinx Solution Center for XST (Xilinx Answer 38927). The Xilinx Solution Center for XST is available to address all questions related to XST. Whether you are starting a new design or troubleshooting a problem, use the Solution Center for XST to guide you to the right information.
Solution
The XST report consists of 5 major sections. An error within one section is going to indicate a different type of error\warning.
The 5 major sections include:
HDL Parsing
Elaboration
HDL Synthesis
Advanced Synthesis
Low Level Synthesis
HDL Parser error\warning: The HDL Parser compiles one module/entity at a time. Errors are commonly, but not limited to syntax errors. The HDL Parser also checks for type mismatches within the module. These errors are generally labeled 'HDLCompiler'. Some commonly found errors\warnings may include:
See (Xilinx Answer 37596) for help resolving "HDLCompiler:114 - "%s" Line #: /* in comment" warnings. See (Xilinx Answer 38231) for help resolving "HDLCompiler:696: Part-select direction is opposite from prefix index direction" errors. See (Xilinx Answer 38232) for help resolving "HDLCompiler:718: Port connections cannot be mixed ordered and named" errors.
Elaboration error\warning: Elaboration stitches together all the HDL that was created. Computation from Parameters/Generics are made and checked to be valid. Errors in this section are commonly, but not limited to issues with interpreting the logic from the HDL. Some commonly found errors\warnings may include:
See (Xilinx Answer 38213) for help resolving "HDLCompiler:634 - Net <net name> does not have a driver" warnings. See (Xilinx Answer 38210) for help resolving "HDLCompiler:679 - Case statement is complete. others clause is never selected" warnings. See (Xilinx Answer 38215) for help resolving "HDLCompiler:91 -Signal missing in the sensitivity list is added for synthesis purposes" warnings. See (Xilinx Answer 38216) for help resolving "HDLCompiler:1007 -element index %d into %s is out of bounds" warnings. See (Xilinx Answer 38233) for help resolving "HDLCompiler:508 - illegal recursive module instantiation of %s" errors. See (Xilinx Answer 40119) for help resolving "HDLCompiler:1156 - Formal port does not exist in entity" errors. See (Xilinx Answer 39980) for help resolving "HDLCompiler:89 - <instance name> remains a black-box since it has no binding entity" warnings.
HDL Synthesis error\warning: HDL Synthesis begins to recognize basic macros. Finite state machines are also detected here. Errors in this section of the Synthesis Report are also very rare. It is recommended to look at the previous sections for clues on why this error is occurring.
See (Xilinx Answer 39136) for help resolving "Xst:737 - Found 1-bit latch for signal <send_char_valid>" warnings.
Advanced Synthesis error\warning: Advanced Synthesis combines the basic macros from HDL Synthesis into larger macros. The finite state machines are also assigned an encoding scheme. Errors in this section of the Synthesis Report are also very rare. It is recommended to look at the previous sections for clues on why this error is occurring.
Low Level Synthesis error\warning: Low level Synthesis optimizes entities/modules so that they are optimized for the targeted device. There is also a global optimization that occurs in this stage of synthesis. Very few errors occur in Low Level Synthesis.
See (Xilinx Answer 14264) for help resolving "Xst:528 - Multi-source in Unit <instance name> on signal <signal name>" errors. See (Xilinx Answer 14265) for help resolving "Xst:529 - Sources are: <inst1>:<sig>, <inst2>:<sig>" warnings.
Design Summary: The Design Summary includes four different reports: Primitive and Black Box Usage, Design Utilization Summary, Partition Resource Summary, and Timing Report.
See (Xilinx Answer 40788) for help determining why the PAR Utilization Summary does not match the XST Design Utilization Summary.