You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
UG454 - Spartan-3A DSP Starter Platform User Guide (Table 3 corrections)
The Spartan-3A DSP Starter Platform User Guide v1.1 (UG454) lists the FPGA DDR2 interface pinout in Table 3 (page 11 and 12).
FPGA pin number M8 is listed twice, as is DDR2 signal FPGA_DDR_LDM_0.
Is this correct?
There are typos in Table 3 of the Spartan-3A DSP Starter Platform User Guide v1.1 (UG454).
- The DDR2 Signal FPGA_DDR_A1 should have the associated FPGA pin number M9 (not M8).
- The DDR2 Signal associated with FPGA pin Number V1 should be FPGA_DDR_UDM_0.
- The DDR2 Signal FPGA_DDR_UDQS_1 should have the associated FPGA pin number R3 (not R2).
Was this Answer Record helpful?
Linked Answer Records
Associated Answer Records
|Boards & Kits
- XtremeDSP Starter Platform - Spartan-3A DSP 1800A Edition