The GCLK0 pin can glitch Low when the device exits the final state of the Start-Up sequence.
The glitch does not occur if one of the following I/O Standards is used:
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
34856 | Design Advisory Master Answer Record for Spartan-6 FPGA | N/A | N/A |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
40000 | Spartan-6 - 13.4 Known Issues Related to Spartan-6 FPGA | N/A | N/A |
AR# 40387 | |
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Date | 05/20/2012 |
Status | Active |
Type | Design Advisory |
Devices |