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  3. AR# 40408: 12.4 Bitgen - ERROR:PhysDesignRules:2175 - Invalid configuration ... When the DSP48E1 AREG attribute is set to 1,? the CEA2 input pin should have active or VCC connectivity

AR# 40408

12.4 Bitgen - ERROR:PhysDesignRules:2175 - Invalid configuration ... When the DSP48E1 AREG attribute is set to 1,? the CEA2 input pin should have active or VCC connectivity

Description

According to the DSP User Guide, it is possible to set AREG = 1 and use the A1 register only. Furthermore, to save power, it is possible to set CEA2 = 0.

Map:
WARNING:PhysDesignRules:2175 - Invalid configuration (incorrect pin connections
and/or modes) on block:<DSP_Slice>:<DSP48E1_DSP48E1>. When the DSP48E1 AREG
attribute is set to 1, the CEA2 input pin should have active or VCC
connectivity.

BitGen:
ERROR:PhysDesignRules:2175 - Invalid configuration (incorrect pin connections
and/?or modes) on
block:<Ports.0.PortTop/?TxStrEng/?Chksum/?TSAdj/?MultAdd>:<DSP48E1_?DSP48E1>.
When the DSP48E1 AREG attribute is set to 1,? the CEA2 input pin should have
active or VCC connectivity.

The user guide claims this is a valid configuration. Why are the warnings/errors occurring and how can I avoid this error?

Solution

This is a known issue with the Physical DC. It has been resolved in ISE Design Suite 13.1.

To work around this issue in 12.x, disable DC checks in Bitgen. This can be done by using the -d switch.

Note: This disables DC errors that can potentially result in damages on the device. Use this workaround only when all Physical DC warnings in Map have been acknowledged and addressed.
AR# 40408
Date 04/08/2011
Status Active
Type General Article
Devices
  • Virtex-6 SXT
  • Virtex-6 CXT
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  • Virtex-6 LX
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Tools
  • ISE Design Suite - 12.4