We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 4041

V1.5.x CORE Generator, NGDBuild, (Virtex block RAM) - "ERROR: BASNB Pin mismatch". I cannot select the netlist bus delimiter format if one of my selections is VHDL or Verilog Instantiation Template.


Keywords: CORE Generator, COREGen, bus netlist format, delimiter, VHDL, Verilog

Urgency: Standard

General Description:
If one of your selections under Options->Core Generator Options is
VHDL or Verilog Instantiation Template, CORE Generator v1.5.x
does not allow you to select anything other than B as the bus
netlist format for the CORE Generator EDIF Implementation Netlist.


This is a known problem.

The M1.5 version of CORE Generator assumes that the bus delimiter
must be "<>" in the .EDN file it generates if either Verilog or VHDL
instantiation templates are selected as desired outputs.

The work-around requires two steps:

1. First select only the "EDIF Implementation Netlist"
option as the desired output and set the bus delimiter to
the required format, then generate the module once.

If you are generating a Virtex Block RAM, you will also need
to manually back the EDIF file that is generated in this step
to a different file name.

2. For the second iteration, *deselect* "EDIF
Implementation Netlist" FIRST to avoid overwriting the EDIF
generated the first time around, select "Verilog
(or VHDL) Behavioral Simulation Model" and/or "Instantiation
Template" for the output format, then generate the module

If you are trying to generate the Virtex Block RAM, you
cannot generate HDL outputs without also selecting the EDIF
Implementation Netlist, so select both, generate the module,
then copy back the renamed EDIF file generated in step 1
to your original module name.

This problem is fixed in the COREGen v1.5.2, which is bundled
together with the A1.5isp1 and F1.5isp1 Service Packs. These
two service packs are available as of Feb. 11 and may be
downloaded from this location:


The required EDIF bus delimiters are listed below for
some common CAE platforms:

Cadence: B
Exemplar: B(I)
Mentor: B[I]
Synplicity: B(I) if not using "syn_noarrayports" attribute, otherwise
Synopsys: B

For further information about Synplify requirements for bus notation,
please refer to (Xilinx Solution 4272).
AR# 4041
Date 02/11/2001
Status Archive
Type General Article