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AR# 40453

MIG 7 Series v1.1 - Can clk_ref_i, sys_rst, and status signals be located in memory banks (Data or Address/Control banks)?

Description

In MIG 7 Series v1.1, the bank selection algorithm forces users to assign the ref clock (clk_ref_i), sys_rst, and status signals (calib_complete and error) to non-memory banks.

Is this required, or can these signals be assigned to a memory bank (Data or Address/Control bank) if free pins are available?

Solution

If free pins are available, it is possible to place clk_ref_p and clk_ref_n in a memory bank, but the status signals are not allowed to be. 

Note: If these signals are combined in a memory bank, compatible I/O standards are required.

Starting in the 13.2 software release, MIG allows system clock pins in memory banks.

However, there are no plans to allow status pins.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40050 MIG 7 Series v1.1 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40050 MIG 7 Series v1.1 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
AR# 40453
Date Created 02/10/2011
Last Updated 08/12/2014
Status Active
Type General Article
Devices
  • Kintex-7
  • Virtex-7
Tools
  • ISE Design Suite - 13.1
IP
  • MIG