In MIG 7 Series v1.1, the bank selection algorithm forces users to assign the ref clock (clk_ref_i), sys_rst, and status signals (calib_complete and error) to non-memory banks.
Is this required, or can these signals be assigned to a memory bank (Data or Address/Control bank) if free pins are available?
If free pins are available, it is possible to place clk_ref_p and clk_ref_n in a memory bank, but the status signals are not allowed to be.
Note: If these signals are combined in a memory bank, compatible I/O standards are required.
Starting in the 13.2 software release, MIG allows system clock pins in memory banks.
However, there are no plans to allow status pins.