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FPGA Express: Constraints GUI uses lower level heirarchical clock name
Keywords: Foundation, fpga, express, heirarchical, VHDL, HDL, clock, name,
When using FPGA Express, the Express Constraints GUI shows the heirarchy and
lower level clock name instead of the top level clock port name.
This does not affect the netlist, as the net name in the .xnf file will be
<clk_port>_BUFGed. All constraints entered through the GUI are correctly
entered into the netlist.
Users should label all clocks that trace through the heirarchy with the same
name. This will aid the user in determining the clock needed in the Express
Example: If two clocks are used in the design (clk40M and clk60M), all clocks
in the lower levels should use the same name to which they are port mapped.
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