When I generate an IBERT core targeting a Virtex-6 LXT and specify the ML605 board, core generation fails and the followingwarning messages occur:
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_U_TO_D = FROM U_CLK TO D_CLK TIG ;> [ibert_core.ucf(36)]: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' constraint named 'U_CLK'.
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;> [ibert_core.ucf(37)]: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' constraint named 'J_CLK'.
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;> [ibert_core.ucf(38)]: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' constraint named 'J_CLK'.
INFO:ConstraintSystem - The Period constraint <NET "ibert_sysclock" PERIOD = 200.0 MHz;> [ibert_core.ucf(83)], is specified using the Net Period method which is not recommended. Please use the Timespec PERIOD method.
WARNING:NgdBuild:1012 - The constraint <INST /example_chipscope_ibert/EXPANDED/example_chipscope_ibert/U_SYSCLOCK_IBUFDS
IOSTANDARD = "DEFAULT"> is overridden on the design object U_SYSCLOCK_IBUFDS by the constraint <INST "U_SYSCLOCK_IBUFDS" IOSTANDARD = LVDS_25;> [ibert_core.ucf(80)].
Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'U_ICON' with type 'chipscope_icon_1' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'chipscope_icon_1' is not supported in target 'virtex6'.
ERROR:NgdBuild:456 - logical net 'CONTROL0<3>' has both active and tristate drivers...
Active driver(s) of net 'CONTROL0<3>':
'Q' pin on block
'U_CHIPSCOPE_IBERT/U0/U_IBERT_CORE/U_XSDB_MSTR/U_VHD_CHIPSCOPE_ICON2XSDB_MSTR BR/U_ICON_INTERFACE/icn_cmd_dout' ( FD )
Tristate driver(s) of net 'CONTROL0<3>':
'CONTROL0<3>' pin on block 'U_ICON' ( chipscope_icon_1 )
How do I work around this issue?
This issue occurs when youchoose the ml605 bank113fmchpc board from the Board Settings drop-down.
This issue is scheduled to be resolved in the ChipScope Pro 13.2 tool. In the meantime, you can work around this issue using the following two possibilities:
Modify the component names and rerun implementation manually
Manually set up the IBERT core rather than choosing the board settings