You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
14.x Virtex-7 - Design does not meet timing on Virtex-7 while design meets timing on Virtex-6 device
I have a design that does not meet timing in a Virtex-7 device while the same design does meet timing on a Virtex-6 device.
How can I meet timing on the Virtex-7 device.
You cannot compare apples to apples between a Virtex-6 and Virtex-7 devices. They will have completely different timing numbers.
Virtex-7 FPGAis not in production and so the timing numbers will change.
In this case, by running some smartxplorer runs, we were able to find a run that actually met timing on the Virtex-7 device.
Was this Answer Record helpful?