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AR# 40492

14.x Virtex-7 - Design does not meet timing on Virtex-7 while design meets timing on Virtex-6 device


I have a design that does not meet timing in a Virtex-7 device while the same design does meet timing on a Virtex-6 device.

How can I meet timing on the Virtex-7 device.


You cannot compare apples to apples between a Virtex-6 and Virtex-7 devices. They will have completely different timing numbers.

Virtex-7 FPGAis not in production and so the timing numbers will change.

In this case, by running some smartxplorer runs, we were able to find a run that actually met timing on the Virtex-7 device.
AR# 40492
Date 05/16/2012
Status Active
Type Design Advisory
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
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  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
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