UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
Page Bookmarked
  1. Xilinx - All Programmable
  2. Support
  3. AR# 40501: MIG v3.3-3.61 Virtex-5 DDR2 SDRAM - Missing signal from sensitivity list

AR# 40501

MIG v3.3-3.61 Virtex-5 DDR2 SDRAM - Missing signal from sensitivity list

Description

When simulating a MIG Virtex-5 DDR2 design using ModelSim with the Synthesis check turned on, the following warning message is displayed:

Warning: /vobs/mlhw/puma/patriot/hw/ddr2_if/rtl/ddr2_phy_init.vhd(1174): (vcom-1400) Synthesis Warning: Signal "cal4_started_r" is read in the process but is not in the sensitivity list.



Can this warning message be safely ignored?

Solution

Yes, this warning message is safe to ignore.

It can also be worked around by adding "cal4_started_r" to the sensitivity list in phy_init.v/.vhd.  
AR# 40501
Date 08/19/2014
Status Active
Type General Article
Tools
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
IP
  • MIG