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AR# 40517

Virtex-6 FPGA GTX Transceiver - Excess current draw on unused transceivers and PCIe detect failures


Starting in ISE Design Suite12.1, any unused GTX Transceivers in a Virtex-6 FPGA automatically have a macro inserted as discussed in (Xilinx Answer 35055). Depending on the use case, the termination settings used by this macro can cause unexpected behavior in hardware, including PCIe link training issues and small additional current draw (50 mA per unused transceiver).This Answer Record describes how to modify the termination settings to avoid these issues.


The GTX attributes RCV_TERM_VTTRX and RCV_TERM_GND control the termination voltage at the RX serial pins. The auto-inserted macro currently sets RCV_TERM_VTTRX = TRUE and RCV_TERM_GND = FALSE and needs to be modified so that RCV_TERM_VTTRX = FALSE and RCV_TERM_GND = FALSE. The FPGA Editor can be used to modify RCV_TERM_VTTRX to FALSE by following these steps:

  1. Open the placed and routed ".ncd" file in theFPGA Editor and find a GTX that was left uninstantiated in the original design. It should resemble the following:

  2. Click the "editmode" button on the right side of the screen to put theFPGA Editor into Read Write mode.
  3. Click on the GTX_DUAL that needs to be edited, and click the "editblock" button on the right side of the screen.
  4. Find the RCV_TERM_VTTRX box (near the bottom of the screen) and check the "FALSE" button as shown below:

  5. Repeat steps 3 and 4 for all remaining GTXE1 primitives that have utilized the macro.
  6. Click on the Save icon in the upper left hand side of the screen to save the modified .ncd file.
  7. To generate a bit file, the Tools->Run Bitgen menu item can be used. It will ask for the name of the bitfile to be generated and whatever bitgen options need to be used.
AR# 40517
Date 10/10/2012
Status Active
Type General Article
  • Virtex-6 SXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 CXT