AR# 40529


Spartan-6 - 9K Block RAM Initialization Not Supported (List of Affected IP)


Block RAM used in the 9K mode (RAMB8BWER) can fail to initialize user specified data or default values (all zeros) during configuration in all Spartan-6devices.

Based on the selected IP Parameters, the cores listed below might use a block RAM in 9K mode and need to use the default or pre-initialized values.

If you are using one of the IP listed below, you should review the MAP report to see if your design is using the RAMB8BWER.  

As of ISE Design Suite 13.1, designs containing 9K block RAM will see a physical DRC warning in MAP and in BitGen.

If you see this warning and are using one of the IP listed below then your design does contain a RAMB8BWER, and you should see the Spartan-6 Errata (including EN148) and (Xilinx Answer 39999) for more details on the Spartan-6 9k block RAM initialization issue.


System Logic DSP IP Horizontal
  • Direct Digital Synthesizer Compiler (DDS Compiler)
  • DUC/DDC Compiler
  • Fast Fourier Transform (FFT)
  • FIR Compiler
  • Multiplier
DSP IP Digital Communications
  • Digital Pre-Distortion (DPD)
  • DVB S2 FEC Encoder
  • Interleaver/De-Interleaver
  • LTE DL Channel Encoder
  • Reed Solomon Decoder
  • Reed Solomon Encoder
  • Viterbi Decoder
Multimedia Video And Imaging
  • Color Filter Array Interpolation
  • Defective Pixel Correction
  • Gamma Correction
  • Image Edge Enhancement
  • Image Statistics Engine
  • Video Object Segmentation
  • Video On Screen Display
  • Video Scaler
  • Triple-Rate SDI
  • CPRI

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
39999 Design Advisory for Spartan-6 FPGA - 9K Block RAM Initialization Support N/A N/A

Associated Answer Records

AR# 40529
Date 05/12/2014
Status Active
Type General Article
IP More Less
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