Description

Solution

For designs with multiple MCBs per side, MIG generates an implementation that has the MCBs sharing the same clock resources.

For more information on this requirement, see the "Clocking" section in the Spartan-6 FPGA Memory Controller User Guide (UG388). 

However, in the MIG 3.7 Verilog example design, different clocks are mapped to the user interface of the two controllers. 

While one of them is coming from the nearby PLL, the other one is not connected resulting in a non-functional user interface. 

To work around the issue, see the instructions below.

Work-around for any two MCBs on the left side of the FPGA:

The two MCBs on the left side of a Spartan-6 device are referred to as C3 and C4. 

MIG generates clocking resources with the prefix C3 when both the controllers on the left side are enabled. 

Therefore, the user interface clock on the left side is c3_clk0 and the following code should be added to the example_top module:

wire c4_clk0;
assign c4_clk0 = c3_clk0;

Work-around for any two MCBs on the right side of the FPGA:

The two MCBs on the right side of a Spartan-6 device are referred to as C1 and C5. 

MIG generates clocking resources with the prefix C5 when both the controllers on the left side are enabled. 

Therefore, the user interface clock on the left side is c5_clk0 and the following code should be added to the example_top module:

wire c1_clk0;
assign c1_clk0 = c5_clk0;

Work-around for all four MCBs being used in the FPGA:

The following code should be added to the example_top module:

wire c4_clk0;
wire c1_clk0;
assign c4_clk0 = c3_clk0;
assign c1_clk0 = c5_clk0;

This issue is fixed in ISE Design Suite 13.2.

Linked Answer Records

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