We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 40595

7 Series Integrated Block for PCI Express - x8 Gen 1 and x4 Gen 2 designs using 128-bit interface do not simulate


Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 40469).

A x8 Gen1 or x4 Gen2 design using the 128-bit interface does not link up during simulation.

Note: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


This is due to incorrect attribute settings and a port width mistake in the root port simulation design.

Tocorrect this problem,edit the "board.v" file found in the generated core's simulation/functional/ directory.

In the instance of xilinx_pcie_2_1_rport_v7, make the following attribute modifications:

Change TRN_DW from TRUE to FALSE
Change USER_CLK2_DIV2 from True to FALSE

In the simulation/dsport directory, edit pcie_2_1_rp_v7.v and make the following modifications:

Change the trn_rd and trn_td ports from [127:0] to [63:0]
Change trn_rrem and trn_trem from [1:0] to just a single bit (i.e., delete the "[1:0]" designation).

Revision History
12/06/2011 - Added version resolved reference to AR 40469
03/01/2011 - Initial release

Linked Answer Records

Master Answer Records

Associated Answer Records

AR# 40595
Date 05/20/2012
Status Active
Type Known Issues
  • Kintex-7
  • Virtex-7