I am trying to generate a MIG DDR3 core in the PlanAhead tool and instantiate it into a VHDL top-level design.
However, even though the IP Catalog HDL type is set to Auto, MIG does not open and the following error occurs:
Why does this occur?
MIG 3.3 does not support VHDL.
However, as the IP Catalog HDL type is set to Auto, even though the top-level RTL source is VHDL, MIG should still be able to output a Verilog version of the design so that it can be instantiated in the VHDL top-level in the PlanAhead tool.
To work around this issue, set the IP Catalog HDL type to Verilog (instead of Auto) to create the MIG IP core.