AR# 40630

Description

This Answer Record contains the Release Notes for the LogiCORE IP RXAUI v2.1 Core, which was released in the 13.1 ISEsoftware, and includes the following:

• New Features
• Supported Devices
• Bug Fixes
• Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide.

Solution

New Features

• ISE 13.1 software support
• Kintex-7 FPGA support
• Virtex-7 FPGA support

Supported Devices

• Virtex-7 (Speed Grades -2/-3)
• Virtex-7 XT (7vx485t - Speed Grades -2/-3)
• Kintex-7 (Speed Grades -2/-3)
• Virtex-6 XC LXT/SXT/HXT (Speed Grades -2/-3)

Resolved Issues

• (Xilinx Answer 39493) - LogiCORE IP RXAUI - GTX Transceiver Delay Aligner Errata and Workaround

Known Issues

• (Xilinx Answer 40865) - LogiCORE IP RXAUI v2.1 - Only the FlipChip Virtex-7 and Kintex-7 packages are supported
• (Xilinx Answer 40506) - LogiCORE IP RXAUI v2.1 - Xs areseen in Marvel RXAUI 7 Series timing simulation
• (Xilinx Answer 42674) - LogiCORE IP RXAUI v2.1 - 7-Series Transceiver Wrapper - GTX Port Name Changes in 13.2 ISE Design Suite
• (Xilinx Answer 42850) - RXAUI v2.1 and XAUI v10.1 - Why does the Example Design fail in bitgen when targeting Virtex-7 or Kintex-7 devices
• (Xilinx Answer 42842) - 7-Series GTX Transceiver - PLLREFCLK selection change causing simulation issue in ISE Design Suite 13.1
• (Xilinx Answer 44393) - LogiCORE IP RXAUI v2.1, Kintex-7/Virtex-7 - GTRXRESET pin must be asserted until the PLL has locked
• (Xilinx Answer 43482) -7-Series GTX Transceiver Reset Requirements Upon Configuration

Linked Answer Records

Child Answer Records