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AR# 40632

Virtex-5 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.8 - Release Notes and Known Issues for ISE Design Suite 13.1 and 14.1

Description

This answer record contains the Release Notes for the Virtex-5 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.8, whichwas originally released in ISE Design Suite 13.1 and later tested for ISE Design Suite 14.1,and includes the following:
  • General Information
  • New Features
  • Supported Devices
  • Bug Fixes
  • Known Issues
For installation instructions, general CORE Generator software known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf.

Solution

General Information
  • Supports automatic generation of HDL wrapper files for the Virtex-5 LXT Tri-Mode Ethernet MAC
  • Instantiates user-configurable Ethernet MAC physical interfaces (GMII, MII, RGMII, SGMII and 1000Base-X PCS/PMA configurations are supported)
  • Provides a FIFO-based example design
  • Provides a demonstration testbench for the selected configuration
New Features
  • ISE 13.1 software support
  • ISE 14.1 software support
Supported Devices
  • Virtex-5 XC LXT/SXT/TXT/FXT
  • Virtex-5 XQ LXT/SXT/FXT
Resolved Issues
  • (Xilinx Answer 39190) Virtex-5 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.7 - GTP/GTX Physical DRC failure in MAP

Known Issues Resolved in v1.8 rev1

  • (Xilinx Answer 45916) Virtex-5 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.8 - PhysDesignRules error during MAP when using SGMII or 1000BASE-X modes
Known Issues in v1.8 and v1.8 rev1
  • (Xilinx Answer 34966)Virtex-5 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.7 - Configurations using EMAC0 and EMAC1, each with tri-speed GMII and standard clocking, fail in MAP due to Place error
  • (Xilinx Answer 43338) Virtex-4/Virtex-5/Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Configured for MII, GMII, or RGMII operation at 10 Mbps, MDIO transactions errors can occur
  • (Xilinx Answer 47354) Virtex-4/Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper - Simulation Failure using Cadence IES 11.1

Download Rev1 Update (Included in the Xilinx ISE 14.1 and later software)

The Rev1 update is included in the Xilinx ISE 14.1 and later software, users only need to download it if using Xilinx ISE 13.x. If using Xilinx ISE 13.x to get the Rev1 update to resolve the issue described above, apply the following patch to the Xilinx ISE 13.x software installation:
http://www.xilinx.com/txpatches/pub/swhelp/ise13_updates/ar40632_v5_emac_v1_8_rev1.zip

Install the patch by extracting the contents of the ".zip" archive to the root directory of the Xilinx ISE 13.x software installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.

After installing the patch, regenerate the Virtex-5 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.8 in the 13.x CORE Generator tool.For further information on finding the Xilinx installation and using environment variables, see (Xilinx Answer 11630).

NOTE: You might need system administrator privileges to install the patch if you do not have write permissions to the Xilinxinstallation directory.

AR# 40632
Date Created 02/16/2011
Last Updated 05/16/2012
Status Active
Type Release Notes
Tools
  • ISE Design Suite - 13.1
  • ISE Design Suite - 14.1
IP
  • Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper