UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 40633

Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.5 - Release Notes and Known Issues for ISE Design Suite 13.1

Description

This Answer Record contains the Release Notes for the Virtex-6 FPGA LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v1.5, which was released in ISE DesignSuite 13.1, andincludes the following:
  • General Information
  • New Features
  • Supported Devices
  • Resolved Issues
  • Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf.

Solution

General Information
  • Supports automatic generation of HDL wrapper files for the Virtex-6 FPGA Tri-Mode Ethernet MAC
  • Instantiates user-configurable Ethernet MAC physical interfaces (GMII, MII, RGMII, SGMII, and 1000Base-X PCS/PMA configurations are supported)
  • Provides a FIFO-based example design
  • Provides a demonstration testbench for the selected configuration
  • (Xilinx Answer 33593) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Frequently Asked Questions (FAQ)
  • (Xilinx Answer 38279) Ethernet IP Solution Center
New Features
  • ISE 13.1 software support
Supported Devices
  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
Resolved Issues Known Issues
  • (Xilinx Answer 33195) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Adjusting IDELAYs to meet GMII and RGMII setup and hold requirements
  • (Xilinx Answer 39960) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC - Synopsys VCS back-annotated timing simulations time out
  • (Xilinx Answer 43338) Virtex-4/Virtex-5/Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Configured for MII, GMII, or RGMII operation at 10 Mbps, MDIO transactions errors can occur


Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
39960 Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC - Synopsys VCS back-annotated timing simulations time out N/A N/A
AR# 40633
Date Created 02/25/2011
Last Updated 02/27/2013
Status Active
Type Release Notes
IP
  • Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper