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  3. AR# 40637: Virtex-6 FPGA Integrated Block for PCI Express - DRC Error During Simulation using Provided Root Port Model

AR# 40637

Virtex-6 FPGA Integrated Block for PCI Express - DRC Error During Simulation using Provided Root Port Model

Description

Version Found: v2.2, v1.4
Version Resolved and other Known Issues: See (Xilinx Answer 45723).

When using ISE 13.1 or later softwareto simulatethe wrapper using the provided root port model, simulation will fail with the following error message:

DRC Error : Value of POWER_SAVE[4] should be set to 1'b1 for instance board.RP.rport.pcie_2_0_i.pcie_gt_i.gtx_v6_i.GTXD[0].GTX of GTXE1.

Solution

This erroroccurs due to a new DRC check added inISE 13.1 softwareto ensure users have followed the Virtex-6 GTX workaround fixfound in(Xilinx Answer 39456). If you are using an older version of the core, you must implement this work around. In ISE 13.1 software, once thisworkaround isimplemented, the DRC errors will not happen.

This issues is fixed in the v2.3 or laterfor theAXI-Streaming interface or v1.7 or later for legacy TRN interface wrapper available in ISE 13.1 software.

Revision History
01/18/2012 - Updated; added reference to 45072
03/01/2011 - Initial Release

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
37936 Virtex-6 FPGA Integrated Block Wrapper v1.6 for PCI Express - Release Notes and Known Issues N/A N/A
39353 Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.2 N/A N/A
AR# 40637
Date 05/20/2012
Status Active
Type Known Issues
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )