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AR# 40651

12.2 EDK, MPMC - Slight overshoot might occur on DQS/DQS_n in Virtex-6

Description

When I test a MPMC DDR3 design on my Virtex-6 board, some slight DQS overshoot occurs, even when using ODT.

Solution

DQS starts toggling prior to ODT write termination, overshoot occurs during this period (ODT write termination is turned on ODT on clock cycles after ODT signal is sampled high). The DQS extra beats are functionally "don't care". Refer to (Xilinx Answer 33137) for more information.

To prevent DQS overshoot prior to ODT termination, ODT is to be enabled earlier in a future MPMC version.

This issue is currently scheduled to be fixed starting in EDK 13.2.

AR# 40651
Date Created 02/16/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 LX
  • Virtex-6 LXT
Tools
  • EDK - 11.5
  • EDK - 12.1
  • EDK - 12.2
  • More
  • EDK - 12.3
  • EDK - 12.4
  • EDK - 13
  • EDK - 13.1
  • Less
IP
  • Multi-Port Memory Controller (MPMC)