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  3. AR# 40660: LogiCORE IP Digital Pre-Distortion (DPD) v4.0 - How is the IP affected by the Spartan-6 9K Block RAM Issue?

AR# 40660

LogiCORE IP Digital Pre-Distortion (DPD) v4.0 - How is the IP affected by the Spartan-6 9K Block RAM Issue?

Description

How does the Spartan-6 FPGA 9K Block RAM Initialization issue described in (Xilinx Answer 39999) affect the LogiCORE Digital Pre-Distortion (DPD)?

Refer to Spartan-6 Errata (including EN148) and (Xilinx Answer 39999) for more details on the Spartan-6FPGA 9k block RAM initialization issue.

Solution

The Spartan-6 FPGA 9K Block RAM Initialization issue does affect the DPD IP as the core does use 9K BRAM. Block RAM used in the 9K mode (RAMB8BWER) can fail to initialize user specified data or default values (all zeros) during configuration inall Spartan-6devices. You should review the MAP report to see if your design is using the RAMB8BWER.

If your design does contain a RAMB8BWER, see the Spartan-6 Errata (including EN148) and (Xilinx Answer 39999) for more details on the Spartan-69k block RAM initialization issue. For a detailed list of Digital Pre-Distortion (DPD) Release Notes and Known Issues, see (Xilinx Answer 33521)

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40529 Spartan-6 - 9K Block RAM Initialization Not Supported (List of Affected IP) N/A N/A
39999 Design Advisory for Spartan-6 FPGA - 9K Block RAM Initialization Support N/A N/A
AR# 40660
Date 05/20/2012
Status Active
Type Known Issues
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q
IP
  • Digital Pre-Distortion (DPD)