2. Support
  3. AR# 4067: M1.4 EPLD-FIT Hitop- Dr. Watson for Windows NT: hitop.exe
  4. AR# 40672: LogiCORE IP FIFO Generator- How is the IP affected by the Spartan-6 FPGA 9K block RAM issue?

AR# 40672

LogiCORE IP FIFO Generator- How is the IP affected by the Spartan-6 FPGA 9K block RAM issue?

Description

How does the Spartan-6 FPGA 9K block RAM initialization issue described in (Xilinx Answer 39999) affect the LogiCORE IP FIFO Generator?

For more details on the Spartan-6 FPGA 9k block RAM initialization issue, refer to  Spartan-6 Errata (including EN148) and (Xilinx Answer 39999).

Solution

The FIFO Generator IP core uses 9K block RAM in some configurations. A MAP and BitGen DRC warning is issued if your configuration uses the RAMB8BWER.

Because the FIFO Generator cannot be initialized and is always written to before it has a valid output, the warning can be safely ignored.

AR# 40672
Date 09/10/2019
Status Active
Type General Article
Devices
IP