How does the Spartan-6 FPGA 9K block RAM initialization issue described in (Xilinx Answer 39999) affect the LogiCORE IP FIFO Generator?
For more details on the Spartan-6 FPGA 9k block RAM initialization issue, refer to Spartan-6 Errata (including EN148) and (Xilinx Answer 39999).
The FIFO Generator IP core uses 9K block RAM in some configurations. A MAP and BitGen DRC warning is issued if your configuration uses the RAMB8BWER.
Because the FIFO Generator cannot be initialized and is always written to before it has a valid output, the warning can be safely ignored.
| AR# 40672 | |
|---|---|
| Date | 09/10/2019 |
| Status | Active |
| Type | General Article |
| Devices | |
| IP | |