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Packaging Solution Center

The Packaging Solution Center is available to address all questions related to Packaging. Whether you are starting with part selection, working on layout and design considerations, or even in the assembly process, use the Packaging Solution Center to guide you to the right information.

Design Assistant

Packaging Design Assistant

The Packaging Design Assistant outlines packaging related information based different steps in the process, whether trying to select a part or package, compiling design considerations for a board layout, or looking for more info during assembly.

NOTE: This answer record is part of the Xilinx Packaging Solution Center (Xilinx Answer 40687). The Xilinx Packaging Solution Center is available to address all questions related Packaging.


First, select the design phase where you have a question or are troubleshooting an issue related to your configuration solution. This ensures that the Packaging Design Assistant points you to the information you need to continually move forward with your design.

(Xilinx Answer 40691) Part Selection and Ordering: The part markings are further explained here along with material declaration, explanations of stepping, and device specific packaging common questions are all addressed here.
(Xilinx Answer 40690) Layout and Design Considerations: Issues such as temperature design issues, heat sink selection, and flight time for packages are all explained here.
(Xilinx Answer 40689) Assembly Process: The device reliability information, and moisture and information can all be found here.

Documentation

Packaging Solution Center - Documentation

Please refer to the following documentation when using Xilinx Packaging Solutions.

NOTE: This answer record is part of the Xilinx Packaging Solution Center (Xilinx Answer 40687). Xilinx Packaging Solution Center is available to address all questions related to packaging.


Generic Packaging Solutions

Virtex-6

Spartan-6


Design Advisories

Design Advisory Master Answer Record for Virtex-6 FPGA

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Design Advisory covers the Virtex-6 FPGA and related issues that impact Virtex-6 FPGA designs.


Design Advisory Alerted on April 8, 2013:
04/05/2013 (Xilinx Answer 45166) Updated Design Advisory for Virtex-6 FPGA GTH Transceiver to include the updated RX_P1_CTRL attribute value 

Design Advisory Alerted on August 13, 2012:
08/15/2012 (Xilinx Answer 51145) Design Advisory - 14.2 iMPACT - Indirect Programming on Virtex-6 causes tool to crash without warning

Design Advisory Alerted on May 21, 2012:
05/17/2012 (Xilinx Answer 47938) Design Advisory for Virtex-6 FPGA - Designs usingOPAD Tioop/Tiotpmust be re-run through timing analysis

Design Advisory Alerted onFebruary 13, 2012:
01/25/2012 Update to(Xilinx Answer 42444) Design Advisory for Virtex-6 FPGA - Designs using 18K/36K block RAM or 18K/36K FIFO must be re-run through timing analysis

Design Advisory Alerted on January 16, 2012:
01/13/2012 (Xilinx Answer 45166) Design Advisory for Virtex-6 GTH Transceiver on burst of errors at startup and RXRECCLK not toggling at startup

Design Advisory Alerted on December 19, 2011:
12/13/2011(Xilinx Answer 43591)Updated Design Advisory for Virtex-6 FPGA GTH Transceivers on RXBUFRESET-related initialization sequence and BUFFER_CONFIG_LANEx issues to include fix information for ES Silicon

Design Advisory Alerted on November 21, 2011:
11/21/2011 (Xilinx Answer 44174)Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup

Design Advisories Alerted onSeptember 19, 2011:
09/19/2011(Xilinx Answer 43829)Design Advisory for Virtex-6 FPGA GTH Transceivers -Incorrect RXBUFRESET connections in the wrapper in x4 Mode

Design Advisories Alerted onAugust 22, 2011:
08/22/2011(Xilinx Answer 43591)Design Advisory for Virtex-6 FPGA GTH Transceivers - Updates required to address RXBUFRESET-related initialization sequence and BUFFER_CONFIG_LANEx issues

Design Advisories Alerted onAugust 8, 2011:
08/08/2011(Xilinx Answer 43346) Design Advisory for Virtex-6 GTH - Recommendation for Non-retimed 10G+ Optical Interfaces (e.g., SFP+ and QSFP)
08/08/2011 (Xilinx Answer 42682)Design Advisory for Virtex-6 FPGA - 13.x iMPACT - eFUSE key programming incorrect when target FPGA is not the only device in the JTAG chain

Design Advisories Alerted onJuly 11, 2011:
07/08/2011 (Xilinx Answer 42444) Design Advisory for Virtex-6 FPGA - Designs using 18K/36K block RAM or 18K/36K FIFO must be re-run through timing analysis
07/07/2011 (Xilinx Answer 41821) Design Advisory for Virtex-6 FPGA - BitGen Option -g Next_Config_Addr: Default Value Changed
07/07/2011 (Xilinx Answer 41099)Design Advisory for Virtex-6 FPGA - Synchronous FIFOs must have reset synchronized to RDCLK/WRCLK

Design Advisories Alerted onJuly 6, 2011:
07/01/2011 (Xilinx Answer 42444) Design Advisory for Virtex-6 FPGA - Designs using 18K/36K block RAM or 18K FIFO must be re-run through timing analysis
06/30/2011 (Xilinx Answer 42682)Design Advisory for Virtex-6 FPGA - 13.x iMPACT - eFUSE key programming incorrect when target FPGA is not the only device in the JTAG chain
04/11/2011 (Xilinx Answer 41099) Design Advisory for Virtex-6 FPGA - Synchronous FIFOs must have reset synchronized to RDCLK/WRCLK

Design Advisories Alerted on March 21, 2011:
03/18/2011 (Xilinx Answer 40885) Updated Design Advisory for Virtex-6 FPGA Production GTH Transceivers to include GTH TXUSERCLKOUT/RXUSERCLKOUT operational guideline.

Design Advisories Alerted on March 7, 2011:
03/04/2011 (Xilinx Answer 40885) Design Advisory for Virtex-6 FPGA - Production GTH Transceivers

Design Advisories Alerted on October 18, 2010:
10/11/2010 (Xilinx Answer 38132) Virtex-6 FPGA MMCM Design Advisory - MMCM BANDWIDTH attribute requirement
10/11/2010 (Xilinx Answer 38133) Virtex-6 FPGA MMCM Design Advisory - Restriction for DIVCLK_DIVIDE value when Fclkin > 315 MHz
09/27/2010 (Xilinx Answer 38134) Virtex-6 Configuration - PROGRAM_B pin held Low prior to power up does not delay configuration
09/07/2010 (Xilinx Answer 36642) Virtex-6 System Monitor - Maximum DCLK frequency revised down to 80 MHz

Design Advisories Alerted on August 30, 2010:
08/27/2010 (Xilinx Answer 37667) Virtex-6 FPGA -1L Industrial Grade Vccint Specification Change

Design Advisories Alerted on March 22, 2010:
03/19/2010 (Xilinx Answer 34859) Virtex-6 FPGA Block RAM Design Advisory - Address Space Overlap
02/11/2010 (Xilinx Answer 33849) Virtex-6 FPGA MMCM - New Requirements for all MMCMs, VCO minimum frequency, and CLKBOUT_MULT_F values
01/22/2010 (Xilinx Answer 34164) Virtex-6 11.4 ISE - Virtex-6 FPGA designs must be re-run through implementation in ISE 11.5 or later software

Revision History:

04/05/2013 - Updated Answer Record 45166
09/24/2012 - Minor update; no change to content
08/09/2012 - Added Answer Record 51145
05/17/2012 - Added Answer Record 47938
02/13/2012 - Added Update to Answer Record 42444
01/13/2012 - Added Answer Record 45166
12/13/2011 - Updated Answer Record 43591
12/12/2011 - Updated title for 44174
11/21/2011 - Added Answer Record 44174
09/15/2011 - Added Answer Record 43829
08/18/2011 - AddedAnswer Record 43591
08/01/2011 - Added Answer Record 43346, updated Answer Record 42682
07/07/2011 - Added Answer Record 41821, updated Answer Records 42444 and 41099
07/05/2011 - Added Answer Record 42444, updated Answer Record 41099
06/30/2011 - Added Answer Record 42682
03/18/2011 - Updated Answer Record 40885
03/04/2011 - Added Answer Record 40885
10/14/2010 - Added Answer Records 38134, 36642
10/12/2010 - Added Answer Records 38132, 38133
08/27/2010 - Added Answer Record 37667
03/19/2010 - Initial Release


Answer Number Answer Title Version Found Version Resolved
45166 Design Advisory for Virtex-6 FPGA GTH Transceiver - Incorrect RX_P1_CTRL attribute can cause undesirable RX behavior N/A N/A
43829 Design Advisory for Virtex-6 FPGA GTH Transceivers - Incorrect RXBUFRESET connections in the wrapper in x4 mode N/A N/A
42444 Design Advisory for Virtex-6 FPGA - Designs using 18K/36K block RAM or 18K/36K FIFO must be re-run through timing analysis N/A N/A
41821 Design Advisory for Virtex-6 BitGen Option Change Can Cause Configuration Failures for Bit Files Generated in 13.2 Where 13.1 Files Worked N/A N/A
41099 Design Advisory for Virtex-6 FPGA - Synchronous FIFOs must have reset synchronized to RDCLK/WRCLK N/A N/A
38134 Design Advisory for Virtex-6 Configuration - PROGRAM_B pin held Low prior to power up does not delay configuration N/A N/A
38133 Virtex-6 FPGA MMCM Design Advisory - Restriction for DIVCLK_DIVIDE value when Fclkin > 315 MHz N/A N/A
38132 Virtex-6 FPGA MMCM Design Advisory - MMCM BANDWIDTH attribute requirement N/A N/A
37667 Virtex-6 FPGA -1L Industrial Grade Vccint Specification Change N/A N/A
34859 Virtex-6 FPGA Block RAM Design Advisory - Address Space Overlap N/A N/A
47938 Design Advisory for 14.1 Timing Analysis Virtex-6 - Tioop/Tiotp values have increased in the analysis of OFFSET OUT and FROM:TO constraints N/A N/A
44174 Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup N/A N/A
33849 Virtex-6 FPGA MMCM - New Requirements for all MMCMs, VCO minimum frequency, and CLKFBOUT_MULT_F values N/A N/A
34164 Virtex-6 11.4 ISE - Virtex-6 FPGA designs must be re-run through implementation in ISE 11.5 or later software N/A N/A
51145 Design Advisory - 14.2 iMPACT - Indirect Programming on Virtex-6 causes tool to crash without warning N/A N/A

Design Advisory Master Answer Record for Spartan-6 FPGA

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System. This answer record lists the Design Advisories that have been communicated for the Spartan-6 FPGA products.

For a complete list of Known Issues for Spartan-6 FPGAs, please see (Xilinx Answer 40000) for ISE Design Suite 13.x and (Xilinx Answer 35180) for ISE Design Suite 12.x.

Design Advisory Alerted on June 19, 2013
06/13/2013 - (Xilinx Answer 56363) - Design Advisory for Spartan-6 FPGAs - JTAG Boundary Scan testing can fail with inverted values seen on pins when the device is configured

Design Advisory Alerted on June 10, 2013
06/06/2013 - (Xilinx Answer 56113) - Design Advisory for Spartan-6 BUFIO2, DIVIDE = 2 Issue

Design Advisory Alerted on April 02, 2013
03/28/2013 - (Xilinx Answer 55037) - Design Advisory for Spartan-3A and Spartan-6: After SelectMAP configuration, when Readback CRC is enabled and an ABORT is triggered spurious failures may be flagged in Readback CRC

Design Advisory Alerted on November 19, 2012:
11/15/2012 - (Xilinx Answer 52716) - Design Advisory for Spartan-6 FPGAs - Configuration Readback including SEM_IP or POST_CRC causes power distribution network noise affecting SelectIO and GTP interfaces

Design Advisory Alerted on February 13, 2012:
02/10/2012 - (Xilinx Answer 46141) - Design Advisory for Spartan-6 - PLL CLKOUT3 Incorrect Phase Shift

Design Advisory Alerted on December 12, 2011:
12/5/2011 - (Xilinx Answer 45011) - Design Advisory for Spartan-6 - BUFPLL LOCK output always high in Bank 2

Design Advisory Alerted on November 21, 2011:
11/21/2011 - (Xilinx Answer 44174) - Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup

Design Advisories Alerted on November 7, 2011:
11/07/2011 - (Xilinx Answer 44192) - Design Advisory for Spartan-6 FPGA Speed File - Updates for Block RAM fMAX in Lower Power -1L Devices
11/07/2011 - (Xilinx Answer 44193) - Design Advisory for Spartan-6 FPGA Speed File - Updates for DCM Phase Alignment

Design Advisories Alerted on September 26, 2011:
09/26/2011 - (Xilinx Answer 44192) - Design Advisory for Spartan-6 FPGA Speed File - Updates for Block RAM fMAX in Lower Power -1L Devices
09/26/2011 - (Xilinx Answer 44193) - Design Advisory for Spartan-6 FPGA Speed File - Updates for DCM Phase Alignment

Design Advisory Alerted on July 11, 2011:
07/07/2011 - (Xilinx Answer 39999) - Design Advisory for Spartan-6 - 9K Block RAM Initialization Support

Design Advisories Alerted on April 18, 2011:
04/18/2011 - (Xilinx Answer 41520) - Design Advisory for Spartan-6 MCB - Removal of VCCINT restrictions to reach maximum DDR3 data rates
04/18/2011 - (Xilinx Answer 41083) - Design Advisory for Spartan-6 IODELAY2 - IODELAY2 Data Rate and Corresponding Bit Error Rates for New Mask Revision Silicon

Design Advisory Alerted on April 04, 2011:
04/04/2011 - (Xilinx Answer 41356) - Design Advisory for Lower Power Spartan-6 -1L Speed Grade - IODELAY2 Support Restricted to Tap 0

Design Advisories Alerted on March 01, 2011:
03/01/2011 - (Xilinx Answer 40387) Design Advisory for Spartan-6 Configuration - GCLK0 input can glitch at the end of configuration
02/23/2011 - (Xilinx Answer 40818) Design Advisory for Spartan-6 SelectIO - INTERM_XX not being appropriately turned on in BitGen for Spartan-6 FPGA inputs

Design Advisory Alerted on December 13, 2010:
12/13/2010 - (Xilinx Answer 39582) Design Advisory for Spartan-6 - When using POST_CONFIG_CRC the INIT_B pin can not be User I/O

Design Advisory Alerted on November 15, 2010:
11/11/2010 - (Xilinx Answer 38733) Design Advisory for Spartan-6 - LX100/LX100T SMAP x16 max CCLK frequency reduction

Design Advisories Alerted on October 18, 2010:
10/13/2010 - (Xilinx Answer 38408) Design Advisory for Spartan-6 - IODELAY2 - early edge delays, late edge delays, and single data bit corruption
10/14/2010 - (Xilinx Answer 35881) Design Advisory for 12.2 Timing/Spartan-6 - DRAM/RAMB instance not analyzed under PERIOD/FROM:TO constraint (Not added to timegroups using TNM)

Design Advisory Alerted on July 19, 2010:
07/19/2010 - (Xilinx Answer 35237) Design Advisory for Spartan-6 FPGA GTP Transceiver - SelectIO to GTP Crosstalk/SSO Guidelines

Design Advisories Alerted on June 14, 2010:
06/14/2010 - (Xilinx Answer 35978) Design Advisory for MIG Spartan-6 MCB - Last word of read burst fails in hardware - bitstream update required for all MCB designs
06/14/2010 - (Xilinx Answer 35976) Design Advisory for MIG Spartan-6 MCB - Design does not come out of reset and requires power-cycle to regain functionality - SW / IP update required
06/14/2010 - (Xilinx Answer 35818) Design Advisory for Spartan-6 FPGA - Memory Controller Block (MCB) Performance Change for DDR2 and DDR3 interfaces

Design Advisory Alerted on April 26, 2010:
04/20/2010 (Xilinx Answer 35237) Design Advisory for Spartan-6 FPGA GTP Transceiver - SelectIO to GTP Crosstalk/SSO Guidelines

Design Advisory Alerted on March 29, 2010:
3/25/2010 (Xilinx Answer 34712) Design Advisory for Spartan-6 FPGA Block RAM - 9K Simple Dual Port (SDP) Block RAM Initialization Incorrect

Design Advisories Alerted on March 22, 2010:
03/19/2010 (Xilinx Answer 34541) Design Advisory for Spartan-6 FPGA Block RAM - 9K Block RAM SDP Port Width Restriction
03/19/2010 (Xilinx Answer 34533) Design Advisory for Spartan-6 FPGA Block RAM - Address Space Overlap

Revision History

06/14/13 - Added 56363
06/06/13 - Added 56113
03/28/13 - Added 55037
11/15/12 - Added 52716
02/10/12 - Added 46141
12/12/11 - Updated title for 44174
12/05/11 - Added 45011
11/21/11 - Added 44174
11/07/11 - Updated 44192 and 44193
09/26/11 - Added 44192 and 44193
07/15/11 - Minor formatting changes
07/11/11 - Added 39999
04/18/11 - Adding 41520 and 41083, also link to 40000 for ISE software 13.1 Known Issues
04/04/11 - Adding 41356
03/01/11 - Added 40387 and 40818
12/13/10 - Added 39582
11/15/10 - Added 38733
10/15/10 - Added 38408 and 35881
07/16/10 - Added 35237
06/14/10 - Added 35978, 35976, and 35818
05/24/10 - Added 35180 for ISE software 12.1 Known Issues
04/26/10 - Added 35237
03/25/10 - Added 34712
03/24/10 - Minor format change
03/22/10 - Initial release 34541 and 34533


Answer Number Answer Title Version Found Version Resolved
45011 Design Advisory for Spartan-6 - BUFPLL LOCK output always high in Bank 2 N/A N/A
41356 Design Advisory for Lower Power Spartan-6 -1L Speed Grade - IODELAY2 Support Restricted to Tap 0 N/A N/A
41083 Design Advisory for Spartan-6 IODELAY2 - IODELAY2 Data Rate and Corresponding Bit Error Rates for New Mask Revision Silicon N/A N/A
39999 Design Advisory for Spartan-6 FPGA - 9K Block RAM Initialization Support N/A N/A
39582 Design Advisory for Spartan-6 - When using POST_CONFIG_CRC the INIT_B pin cannot be User I/O N/A N/A
38733 Design Advisory for Spartan-6 - LX100/LX100T SMAP x16 max CCLK frequency reduction N/A N/A
38408 Design Advisory for Spartan-6 - IODELAY2; Late and Early Edge Delays and Single Data Bit Corruption N/A N/A
35881 Design Advisory for 12.2 Timing/Spartan-6 - DRAM/RAMB instance not analyzed under PERIOD/FROM:TO constraint (Not added to timegroups using TNM) N/A N/A
34712 Design Advisory for Spartan-6 FPGA Block RAM - 9K Simple Dual Port (SDP) Block RAM Initialization Incorrect N/A N/A
40818 Design Advisory for Spartan-6 SelectIO - INTERM_XX not being appropriately Turned On in BitGen for Spartan-6 FPGA inputs N/A N/A
40387 Design Advisory for Spartan-6 Configuration - GCLK0 input can glitch at the end of configuration N/A N/A
44174 Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup N/A N/A
41520 Design Advisory for Spartan-6 MCB - Removal of VCCINT Restrictions to Reach Maximum DDR3 Data Rates N/A N/A
35818 Design Advisory for Spartan-6 FPGA - Memory Controller Block (MCB) Performance Change for DDR2 Interfaces N/A N/A
34533 Design Advisory for Spartan-6 FPGA Block RAM - Address Space Overlap N/A N/A
34541 Design Advisory for Spartan-6 FPGA Block RAM - 9K Block RAM Simple Dual Port (SDP) Data Width Restriction N/A N/A
55037 Design Advisory for Spartan-3A and Spartan-6 - After SelectMAP configuration, when Readback CRC is enabled and an ABORT is triggered, spurious failures might be flagged in Readback CRC N/A N/A
56113 Design Advisory for Spartan-6 BUFIO2, DIVIDE = 2 Issue N/A N/A
56363 Design Advisory for Spartan-6 FPGAs - JTAG Boundary Scan testing can fail with inverted values seen on pins when the device is configured N/A N/A