AR# 40692

Description

Please refer to the following documentation when using Xilinx Packaging Solutions.

NOTE: This answer record is part of the Xilinx Packaging Solution Center (Xilinx Answer 40687). Xilinx Packaging Solution Center is available to address all questions related to packaging.

Solution

Generic Packaging Solutions

• Xilinx Advanced Packaging
• Xilinx: Pb-free and RoHS-compliant Products
• XAPP439 - PCB Pad Pattern Design and Surface-Mount Considerations for QFN Packages
• XAPP426 - Implementing Xilinx Flip-Chip BGA Packages
• XAPP427 - Implementation and Solder Reflow Guidelines for Pb-Free Packages
• WP372 - Lead Free Solder Ball Fragility

Virtex-6

• Virtex-6 Family Package/Device Pinout Files (ASCII)
• Virtex-6 FPGA Packaging and Pinout Specifications
• Virtex-6 FPGA PCB Design Guide
• Device Reliability Report, fourth Quarter 2010
• Design Advisory for the Virtex-6 FPGA Master Answer Record
• XAPP899 - Interfacing Virtex-6 FPGAs with 3.3V I/O Standards
• XAPP1071 - Connecting Virtex-6 FPGAs to ADCs with Serial LVDS Interfaces and DACs with Parallel LVDS Interfaces
• Package Specifications

Spartan-6

• Spartan-6 Family Package/Device Pinout Files (ASCII)
• Spartan-6 FPGA Packaging and Pinouts Specification
• Spartan-6 FPGA PCB Design and Pin Planning Guide
• Device Reliability Report, fourth Quarter 2010
• Design Advisory for the Spartan-6 FPGA Master Answer Record
• Package Specifications

Linked Answer Records

Master Answer Records