AR# 4075: SYNPLIFY: How to infer synchronous (single-port/dual-port) RAM in HDL (Verilog/VHDL)?
SYNPLIFY: How to infer synchronous (single-port/dual-port) RAM in HDL (Verilog/VHDL)?
Keywords: RAM, Synplify, 4000e/x, Virtex
General Description: How to infer RAM in HDL using Synplicity's Synplify?
A RAM structure can be modeled as a 2-dimensional array of registers. Each element of the array is known as a word. Each word can be one or more bits. Synplify automatically detects the RTL description of a synchronous RAM. The RAM is mapped to applicable technology specific RAM cells.
When a RAM block is recognized, Synplify will automatically implement a single-port circuit using RAM16x1S and a dual-port circuit using RAM16x1D primitives.
Note: 1. Use Synplify 5.0 or greater. 2. Initialzing inferred RAM in the HDL code is currently not supported. To do this, you need to find out the instance name of the RAM from Synplify Technology View or from the EDIF netlist and apply INIT attribute in the UCF file. The inferred RAMs are initialized to '0' (zero) by default.