This section of the MIG Design Assistant focuses on FPGA Input Termination Options for Spartan-6 MCB designs.
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Optional on-chip termination features in Spartan-6 FPGAs eliminate complex external board termination schemes for high-speed single-ended signaling, such as those commonly found in memory interfaces. MIG provides several on-chip termination options for the bidirectional memory interface signals: dq, ldqs_p/n, udqs_p/n.
Calibrated Input Termination:
Provides calibrated on-die input termination for DDR2 and DDR3 memory interfaces. Calibration requires two extra pins to be added to the interface: RZQ and ZIO.This option sets the parameterCX_SKIP_IN_TERM_CAL=0 for the top-level MIG generated design, which enables the inputtermination calibration algorithm inthe mcb_soft_calibration module. In addition, the property IN_TERM=NONE is applied to the bidirectional memory interface signals in the MIG generated UCF.
(Xilinx Answer 34055)MIG Spartan-6 FPGA MCB - What are the requirements for the RZQ and ZIO pins?
Un-calibrated Input Termination:
Provides un-calibrated (approximated) on-die input termination resistod to VCCIO and GND for DDR2 and DDR3 memory interfaces.This option sets the parameterCX_SKIP_IN_TERM_CAL=1 for the top-level MIG generated design, whichdisables the inputtermination calibration algorithm inmcb_soft_calibration module.In addition, the property IN_TERM=UNTUNED_SPLIT_25/50/75 (based on the selection in MIG)is applied to the bidirectional memory interface signals in the MIG generated UCF.
Please checkthe"Internal Termination">"On-chip Termination" section ofthe Spartan-6 SelectIO Resources User Guide(UG381) for detailed information about uncalibrated on-die termination. IBIS simulation is recommended for all these situations.
(Xilinx Answer 37081)MIG Spartan-6 MCB - Calibrated Input Termination IBIS Simulation