AR# 40786: Design Assistant for XST - Help with trimmed signals
Design Assistant for XST - Help with trimmed signals
Please refer to this answer record for help resolving XST trimming issues.
Note: This Answer Record is a part of the Xilinx Solution Center for XST (Xilinx Answer 38927). The Xilinx Solution Center for XST is available to address all questions related to XST. Whether you are starting a new design or troubleshooting a problem, use the Solution Center for XST to guide you to the right information.
XST will optimize out Flip-Flops and Latches when all of their inputs are tied to a constant high or low, excluding the clock. XST does this because the output of the Flip-Flop or Latch will have a constant output. This constant output will continue to drive the same logic that was driven before; however, the logic will now be driven by a constant value rather than driven by the Flip-Flop or Latch. Refer to the images below for a helpful explanation.
The example below is intended to illustrate how optimizing one Flip-Flop may optimize out multiple Flip-Flops. Consider the following example where one of the Flip-Flops ties the reset and D pin to a logic low. This results in the output (Q) always being a logic low. This will result with logic described in Figure-2.
Notice in Figure-2 that the two inputs are now constant, similar to inst1 from Figure-1. Again, this results with constant logic on the output (Q) pin. This will ultimately result with one of the inputs of the LUT tied to a logic low, as shown in Figure-3.