Description

When I open the netlist design and use the "Set up ChipScope Wizard" in the PlanAhead tool to add a debug core and probe a net, the operation fails. I see warnings and errors similiar to the following:

"connect_debug_port cs_ila_0_0/TRIG0[get_nets -match_style ucf {module_name\/net_name} ]
WARN: [HD-Tcl3] No nets matched ' module_name\/net_name'.
ERROR: Invalid value for 'nets'"

Solution

The issue is that for flattened designs, net names returned by netlist find operations have a backslash '\' escape character before each hierarchical separator (e.g., 'module_name\/net_name'. This syntax is currently incompatible with the get_nets command when match_style is set to 'ucf'.

There are two work-arounds for this issue:

• Change the netlist_hierarchy attribute to rebuilt before running Synthesis
• Edit the failing Tcl command to change "-match_style ucf" to "-match_style sdc".

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