2. Support
  3. AR# 4081: 4.1i MAP - "FATAL_ERROR:x4kma:x4kmaclkinfo.c:786:1.24 - Clkinfo: sitearray overrun: page1$1p/page1$i135."
  4. AR# 40811: 13.1 ChipScope, PlanAhead - "WARN: [HD-Tcl 3] No nets matched '<connect_debug_port cs_ila_0_0/TRIG0 [get_nets -match_style ucf {module_name\/net_name} ] WARN: [HD-Tcl 3] No n>'. ERROR: Invalid value for 'nets'"

AR# 40811

13.1 ChipScope, PlanAhead - "WARN: [HD-Tcl 3] No nets matched ''. ERROR: Invalid value for 'nets'"

Description

When I open the netlist design and use the "Set up ChipScope Wizard" in the PlanAhead tool to add a debug core and probe a net, the operation fails. I see warnings and errors similiar to the following:

"connect_debug_port cs_ila_0_0/TRIG0[get_nets -match_style ucf {module_name\/net_name} ]
WARN: [HD-Tcl3] No nets matched ' module_name\/net_name'.
ERROR: Invalid value for 'nets'"

What is the issue here and how do I work aroundit?

Solution

The issue is that for flattened designs, net names returned by netlist find operations have a backslash '\' escape character before each hierarchical separator (e.g., 'module_name\/net_name'. This syntax is currently incompatible with the get_nets command when match_style is set to 'ucf'.

There are two work-arounds for this issue:

  • Change the netlist_hierarchy attribute to rebuilt before running Synthesis
  • Edit the failing Tcl command to change "-match_style ucf" to "-match_style sdc".
This issue is scheduled to be resolved in ISE Design Suite 13.2.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40485 13.x ChipScope Pro - Known Issues for the ChipScope Pro 13.x Software N/A N/A
AR# 40811
Date 12/15/2012
Status Active
Type General Article
Tools
IP