UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 40837

Timing Design Assistant - Timing Closure & Constraint Setup

Description

General Answer Records that explain how to setup timing constraints for Timing Closure.

Solution

Register-to Register (PERIOD) related

(Xilinx Answer 18877)- 13.1 Timing Analyzer/Constraint - Using a FF (gate clock) for divide circuitry causes problems with the PERIOD analysis
(Xilinx Answer 16717) - 12.1 Timing Analyzer/Constraint - A PERIOD constraint is not analyzed
(Xilinx Answer 15833) - 12.1 Timing Analyzer/Constraint - How do I add a PERIOD constraint to the N-side of my differential pair?
(Xilinx Answer 6905) - 12.1 Constraints - How do I apply a PERIOD constraint on a DLL/DCM/PLL/MMCM?
(Xilinx Answer 2586) - 12.1 Timing/Constraints, Virtex-4 and newer and Spartan-3 and newer - PLL/DCM Timing Constraints Issues
(Xilinx Answer 14775) -12.1 Timing - How do the timing tools find a relationship between two phase-shifted/multiplied clocks?

Input & Output (OFFSET) related

(Xilinx Answer 31708) - 13.1 Timing Analyzer - When I run an OFFSET analysis in timing analyzer on its own, I receive different results than if I run a full timing analysis
(Xilinx Answer 29189) - 13.1 Timing Analyzer - Why is DCM Phase Shifting ignored when OFFSET ... HIGH | LOW is specified?
(Xilinx Answer 7862) - 12.1 Timing Constraints - How do I specify a CLOCK_TO_OUT/CLOCK_TO_PAD constraint with an internally divided/multiplied clock?
(Xilinx Answer 11589) - 12.1 NGDBuild/Constraint - "ERROR:NGD:635 - Specification "OFFSET=IN <time>ps before <signal_name>" on signal "<problem_signal> (for_INT)" is not valid..."
(Xilinx Answer 4508) - 12.1 Timing Analyzer - How to determine if the downstream device will have a hold time violation? (trce -s min)

Timing Exception (FROM:TO) related

(Xilinx Answer 13920) 12.1 Known Issue - Timing Analyzer - My FROM:TO constraint picks up the wrong paths (TNM)
(Xilinx Answer 34348) 12.x Timing Constraints - How can I exclude cross-domain paths from Timing Analysis?

TNM vs TNM_NET

(Xilinx Answer 17063) - 12.1 Known Issue - Timing Analyzer/Constraint - Derived PERIOD constraints are ignored when the main PERIOD constraint is specified using a "NET" keyword

NET PERIOD vs TIMESPEC PERIOD

(Xilinx Answer 33765) -11.1 Timing Analyzer - NET PERIOD clock arrival times change

Clock driving through BUFGMUX

(Xilinx Answer 20957) - 11.1 Release Note - Timing - Timing Simulation reports setup errors, but Timing Analyzer reports that all is well
(Xilinx Answer 31276) - 11.4 Timing Analyzer - Incorrect clock skew reported
(Xilinx Answer 32445) - 11.1 Known Issue - Timing - Incorrect timing analysis associated with input clocks on BUFGMUX
(Xilinx Answer 15807) - 12.1 Known Issue - Timing Analyzer - Timing reports a very large skew on a global clock between flip-flops with BUFGMUX

TPSYNC

(Xilinx Answer 33904) - 11.3 TRCE/Timing Analyzer (Partial) - FROM:TO TPSYNC not working as expected

PRIORITY

(Xilinx Answer 29242) - 12.1 Release Note, Timing Analyzer - Order of constraints in PCF can produce different timing analyses

Jitter/Uncertainty

(Xilinx Answer 24217) -13.1 Timing - Jitter Information Master Record
(Xilinx Answer 31087) - 12.1 Timing Analyzer - Why does Timing Analyzer show that I have no clock uncertainty?
(Xilinx Answer 10167) - 12.1 Timing - Does Timing Analyzer account for the output jitter of the DCM/DLL/PLL/MMCMs? (Clock Uncertainty)
(Xilinx Answer 23710) - 12.1 TRCE/Timing Analyzer - How is clock uncertainty being calculated now that DCM jitter and phase error have been characterized for Virtex-4 (and newer) devices?

RAM Related

(Xilinx Answer 32756) - 11.4 Timing Analyzer/Trce, Virtex-5 - Extra paths analyzed with respect to block RAM (additional delays through address pins of block RAM)
(Xilinx Answer 32470) - 11.1 Known Issue - Timing Analyzer - Does not analyze paths through Virtex-5 Block Ram

IODELAY

(Xilinx Answer 35479) - 12.1 TRCE/Timing Analyzer - IODELAYE1 DATAOUT is being treated as a synchronous output
(Xilinx Answer 32707) - 12.1 Timing Analyzer - IODELAY Min, Maximum Delay information

GTP, MCB, PCIe

(Xilinx Answer 30449) - 12.1 Timing Analyzer - GTP - How is a PERIOD constraint on REFCLK passed through the GTP_DUAL tile?

Cross Clock Domain Analysis

(Xilinx Answer 13752) - ISE Timing & Constraints - How to constrain clock domain crossing paths

Syntax related

(Xilinx Answer 3753) - 12.1 Constraints - UCF to PCF conversion examples (PERIOD, FROM:TO, LOCs, RPMs)
(Xilinx Answer 2449) - 12.1 Constraints/Timing - Basic User Constraints File (UCF) syntax examples for design placement and timing constraints

AR# 40837
Date Created 04/20/2011
Last Updated 12/03/2014
Status Active
Type General Article
Tools
  • ISE
  • ISE Design Suite