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AR# 40845

LogiCORE IP DSP48 Macro v2.1 - Release Notes and Known Issues for ISE Design Suite 13.1

Description

This Answer Record contains the Release Notes and Known Issues list for the CORE Generator LogiCORE IP DSP48 Macro v2.1. The following information is listed for each version of the core:

  • General Information
  • New Features
  • Bug Fixes
  • Known Issues
  • Technical Support

For the latest core updates, see the product page for LogiCORE IP DSP48 Macro v2.1:
http://www.xilinx.com/products/ipcenter/DSP48_macro.htm

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

General Information

For installation instructions for this release:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

New Features in v2.1

  • ISE 13.1 software support
  • Kintex-7 and Virtex-7 device support
  • Optional separate clock enables and resets for each data and control path

Bug Fixes in v2.1

  • N/A

Known Issues in v2.1

  • N/A

Technical Support

To obtain technical support, create a WebCase; questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow the specified guidelines.

AR# 40845
Date Created 02/23/2011
Last Updated 05/19/2012
Status Archive
Type Known Issues
Tools
  • ISE Design Suite - 13.1
IP
  • DSP48 Macro