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  3. AR# 4084: Synplify - How do I disable clock buffer (BUFG) insertion?
  4. AR# 40847: 13.1 Timing Analysis - Why TRCE does not give any error when Fmax of BUFR is over 300 MHz in a MIG design?

AR# 40847

13.1 Timing Analysis - Why TRCE does not give any error when Fmax of BUFR is over 300 MHz in a MIG design?

Description

According to DS153, Fmax of regional clock tree is 300 MHz. I modified a Virtex-6 CXTMIG example design, and when theBUFR input clock is 800 MHz and the output clock is divided by 2 to 400 MHz, why doesn't TRCE give any error.

Solution

The BUFR component is not included in the PERIOD constraint, so the component switching limit analysis is not done on the component. The workaround is to add the BUFR instance to the PERIOD constraint timegroup.

AR# 40847
Date 12/15/2012
Status Archive
Type General Article