AR# 40875: SPI-4.2 v11.1 - Incorrect Side Band Error signal could be asserted in Transparent Status Mode
SPI-4.2 v11.1 - Incorrect Side Band Error signal could be asserted in Transparent Status Mode
For the SPI-4.2 v11.1 Source Core using Transparent Status Mode, the SRC_BRESP_ERR signal (defined as "write transaction to the Status space has failed")asserts for reads and writes to the status memory space. However, since the status memory does not actually exist in Transparent Mode, it is more appropriate to assert SRC_BRESP_ERR instead, which is defined as the "Read/Write transaction missing a valid address."
This issue is to be resolved in the SPI-4.2 v11.2 core scheduled for release in ISE Design Suite 13.2.