"> AR# 40885: Design Advisory for the Virtex-6 FPGA Production GTH Transceivers

UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 40885

Design Advisory for the Virtex-6 FPGA Production GTH Transceivers

Description

ThisDesign Advisory covers the Production Virtex-6 FPGA GTH Transceiver. Its intent is to address the updates to Production Silicon.

The CES errata within this advisory refers to the Virtex-6FPGA HX255T, HX380T, and HX565T CES Errata (EN157):
https://secure.xilinx.com/webreg/clickthrough.do?cid=152984&license=Disclaimer

Solution

CES Errata- Supported PCB Trace Characteristics

For Production Silicon, this has been updated to channels in the 7-8 dB Insertion Loss Range with no TX Emphasis. This updateisavailable in the next revisionofVirtex-6 FPGA GTH Transceiver User Guide (UG371);see the RX Equalization section under Use Mode - Channel Loss <= 7-8 dB with no TX Emphasis sub-section.

CES Errata- RX Equalization Auto-Adaptation

For Production Silicon, this has been updated to using the Adaptation in Auto Mode. This update and details regarding it are available in the next revision of Virtex-6 FPGA GTH Transceiver User Guide (UG371);see the RX Equalization section under Use Mode - Channel Loss <= 7-8 dB with no TX Emphasis sub-section.

CES Errata- Near End PMA Loopback (PMA_LPBK_CTRL_LANE<n>=2'b01 = post-driver)

Thisis not a supported feature.

CES Errata- IEEE Std 1149.6 (AC-JTAG) Test Utilizing GTH Transceivers

For Production Silicon, the GTH Transceivers always need to be configured to use AC-JTAG. This update and details regarding it are available in the next revision ofVirtex-6 FPGA GTH Transceiver User Guide (UG371); see the AC-JTAG section.

CES Errata - Operational Guidelines: GTH TXUSERCLKOUT and RXUSERCLKOUT in 10 Gigabit Ethernet 64B/66B Mode

For Production Silicon,the duty cycle of TXUSERCLKOUT and RXUSERCLKOUT is less than 30%whenthe GTH Transceiver is configured in10 Gigabit Ethernet 64B/66B Mode. TXUSERCLKOUT and RXUSERCLKOUT must be only used with the positive clock edge for fabric logic. The MMCM CLKIN duty cycle specification in theVirtex-6 FPGA Data Sheet: DC and Switching Characteristics (DS152) does not apply to the GTH Transceiver TXUSERCLKOUT and RXUSERCLKOUT. This update is available in the next revision ofVirtex-6 FPGA Data Sheet: DC and Switching Characteristics (DS152)and Virtex-6 FPGA GTH Transceiver User Guide (UG371).

GTH Transceiver Initialization Sequence and Attribute Updates

The most current reset sequence and attribute updates for Production Silicon are available in a Virtex-6 FPGA GTH Transceiver Wizard patch. The details regarding it can be obtained from (Xilinx Answer 40902).

Bitstream Compatibility Between CES vs. Production

CES bitstreams cannot be used with Production Silicon and vice-versa.

GTH Transceiver Reference Clock Maximum Frequency

For Production Silicon, the GTH Transceiver reference clock maximum frequencysupported is700 MHz for -2, -3 speed grades and 645 MHz for -1 speed grade. More details are available in(Xilinx Answer 41022).

To update your Xilinx Alert Notification Preferences, please go to:
http://www.xilinx.com/support/myalerts

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34565 Design Advisory Master Answer Record for Virtex-6 FPGA N/A N/A
38596 Virtex-6 FPGA GTH Transceiver - Known Issues and Answer Records List N/A N/A
AR# 40885
Date Created 02/25/2011
Last Updated 02/28/2013
Status Active
Type Design Advisory
Devices
  • Virtex-6 HXT