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AR# 40899

LogiCORE IP 10-Gigabit Ethernet MAC v10.2 - Timing Simulation timeouts and mismatches seen in certain core configuration for Spartan-6 and Virtex-4 device

Description

Timing Simulation timeouts and mismatches have been seen in certain core configuration for Spartan-6 and Virtex-4 devices. 

Following are the configurations in which timing simulation timeouts and mismatches have been seen and the work-around for these.

Solution

1)  Configuration xgmac_none_qs6lx_simplex_rx:
    FAMILY = qspartan6
    PART = xq6slx150t
    PACKAGE = fg484
    SPEED = 3
    Physical_Interface = Internal
    Statistics_Gathering = false
    Management_Interface = false
    Simplex_Split = Receive_Only

 Work-around: Replace #6399 with #2000 at line.no.682 in demo_tb.v

 

2) Configuration xgmac_xgmii_v4sx_simplex_rx:
    FAMILY = virtex4
    PART = xc4vsx35
    PACKAGE = ff668
    SPEED = 10
    Physical_Interface = XGMII
    Statistics_Gathering = false
    Management_Interface = false
    Simplex_Split = Receive_Only

 Work-around: Replace #6399 with #2000 at line.no.504 in demo_tb.v


3) Configuration xgmac_none_s6lx_simple_tx:
    FAMILY = spartan6
    PART = xc6slx150t
    PACKAGE = fgg484
    SPEED = 3
    Physical_Interface = Internal
    Statistics_Gathering = false
    Management_Interface = false
    Simplex_Split = Transmit_Only

Work-around: Replace #3100 with #2000 at line.no.536 in demo_tb.v

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40627 LogiCORE IP 10-Gigabit Ethernet MAC v10.2 - Release Notes and Known Issues for ISE Design Tools 13.1/13.3/13.3 N/A N/A
AR# 40899
Date Created 03/01/2011
Last Updated 05/23/2014
Status Archive
Type General Article
IP
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