We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 40909

7 Series FPGA Integrated Block v1.1 for PCI Express - Simulation takes a long time to link up using provided example design


Due to an assignment mistake in the 7 Series Integrated Block Wrapper, simulation using the provided example design takes about 75 microseconds to link up.


This can be shortened to about 35 microseconds by modifying the "pcie_gtx_7x.v" filein the wrappers generated source directory.

Change the line:

assign phy_rdy_n = !(&plllkdet[NO_OF_LANES-1:0] & clock_locked);

to the following:
assign phy_rdy_n = (&phystatus_rst[NO_OF_LANES-1:0] & clock_locked);

Revision History
03/10/2011 - Initial release

AR# 40909
Date 05/16/2012
Status Active
Type Known Issues