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AR# 40920

Virtex-6 - 13.x Software Known Issues related to the Virtex-6 FPGA

Description

This Answer Record describes the Known Issues for theVirtex-6 FPGA family used with ISE Design Suite 13.

Solution

The following answer records represent a collection of issues that have been identified in the ISE 13.x Design Tools and are related to Virtex-6 FPGAs. There might be issues that are present and are not listed here. If you discover an issue that is not on this list, please open a WebCase with Xilinx Technical Support.

ISE Design Suite 13.4
Block RAM / FIFO
(Xilinx Answer 45701) Block Memory generator v6.3 - Release Notes and Known Issues for ISE Design Suite 13.4
(Xilinx Answer 45700) FIFO Generator v8.4 - Release Notes and Known Issues for ISE 13.4
GTX/GTH
(Xilinx Answer 45660) Virtex-6 FPGA GTH Transceiver Wizard v1.10 - Release Notes and Known Issues
(Xilinx Answer 45671) Aurora 64B/66B v6.2 - Release Notes and Known Issues for ISE Design Suite 13.4
MIG
(Xilinx Answer 45194) MIG Virtex-6 and Spartan-6 v3.91 - Release Notes and Known Issues for ISE Design Suite 13.4

PCI Express

(Xilinx Answer 45723) Virtex-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface Versions
ISE Design Suite 13.3
Block RAM / FIFO
(Xilinx Answer 42444) Design Advisory - Virtex-6 FPGA designs using 18K/36K block RAM or 18K FIFO must be re-run through timing analysis
(Xilinx Answer 44594) FIFO Generator v8.3 - Release Notes and Known Issues for ISE Design Suite 13.3
GTX/GTH
(Xilinx Answer 44488) Virtex-6 FPGA GTH Transceiver Wizard v1.9 - Release Notes and Known Issues
(Xilinx Answer 45075) Virtex-6 FPGA GTH Transceivers - Wizard v1.9 incorrectly sets GTH Transceivers in PMA loopback by default
(Xilinx Answer 43591)Design Advisory for Virtex-6 FPGA GTH Transceivers - Updates required to address RXBUFRESET-related initialization sequence and BUFFER_CONFIG_LANEx issues
ChipScope/IBERT
(Xilinx Answer 44801) Virtex-6, 13.3, GTX IBERT - Right side GTX transceivers do not link
(Xilinx Answer 44645) 13.3, Virtex-6, ML605 GTX IBERT - "ml605 bank113fmchpc" Board Configuration Setting sets refclk incorrectly

(Xilinx Answer 44963) Virtex-6 CXT, 13.3, GTX IBERT - IBERT GUI in CORE Generator tool does not launch if project option is set to CX75T

(Xilinx Answer 44663) 13.3, Virtex-6, GTX IBERT - Unchecking the "Generate Bitstream" option causes the generation of core to fail
iMPACT
(Xilinx Answer 42682)Design Advisory for Virtex-6 FPGA - 13.x iMPACT - eFUSE key programming incorrect when target FPGA is not the only device in the JTAG chain
MIG
(Xilinx Answer 43130) MIG Virtex-6 and Spartan-6 v3.9 - Release Notes and Known Issues for ISE Design Suite 13.3

Embedded Tri-Mode Ethernet MAC

(Xilinx Answer 44428) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v2.2 (AXI) - Release Notes and Known Issues for ISE Design Suite 13.3

EDK
(Xilinx Answer 45281) 13.3 EDK, AXI_V6_DDRx - Lower memory throughput in EDK 13.3 only
(Xilinx Answer 44088) 13.3 EDK, AXI_V6_DDRx - External memory model simulations fail when using ECC
ISE Design Suite 13.2
Block RAM / FIFO
(Xilinx Answer 42444) Design Advisory - Virtex-6 FPGA designs using 18K/36K block RAM or 18K FIFO must be re-run through timing analysis
(Xilinx Answer 42712) Block Memory generator v6.2 - Release Notes and Known Issues for ISE Design Suite 13.2
BitGen
(Xilinx Answer 41821) Design Advisory Master Answer Record for Virtex-6 BitGen Option -g Next_Config_Addr: Default Value Changed
GTX/GTH
(Xilinx Answer 33475) Virtex-6 FPGA GTX Transceiver - Known Issues and Answer Record List
(Xilinx Answer 38596) Virtex-6 GTH Transceiver - Known Issues and Answer Records List
ChipScope/IBERT
(Xilinx Answer 42843) Virtex-6 GTX IBERT - Some QUADs must always be instantiated for GTs to work correctly
(Xilinx Answer 42837) 13.2 ChipScope IBERT - Default line rate setting for board configuration setting is invalid
(Xilinx Answer 43259) 13.x Virtex-6 GTH IBERT - Problems running half rate speed with the IBERT core
iMPACT
(Xilinx Answer 40562) 12.x/13.x iMPACT - Virtex-6 - Indirect BPI core upper address bits clash with VREF pins
MIG
(Xilinx Answer 41347) MIG Virtex-6 and Spartan-6 v3.8 - Release Notes and Known Issues for ISE Design Suite 13.2

Additional Resources:

To find the generic list of known issues for ISE Design Suite 13.x, see the ISE Design Suite 13: Release Notes Guide (UG631). For information on how to download, install, and obtain a license for ISE Design Suite 13.x, see the ISE Design Suite 13: Installation and Licensing Guide (UG798).

(Xilinx Answer 34565) Design Advisory Master Answer Record for Virtex-6 FPGA

Virtex-6 Errata and Product Change Notification (PCN)

Revision History
01/18/2012 - Updated for 13.4 release
07/06/2011 - Updated for 13.2 release
03/01/2011 - Initial Release

AR# 40920
Date Created 02/28/2011
Last Updated 05/19/2012
Status Active
Type Known Issues
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Less
Tools
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4