UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 40946

LogiCORE CPRI v3.2/v4.1 - What is the smallest Spartan-6 that supports the dual core IP configuration with different line rates?

Description

For the LogiCORE CPRI core v3.2, what is the smallest Spartan-6 FPGA that supports the dual core IP configuration with different line rates?

Solution

The dual core configuration using different line rates of the CPRI core will not fit into an xc6slx25t device. 

This is because the default dual core configuration needs two PLLs that are accessible from the GTPA1 via BUFIOs. 

The xc6slx25t only has one.

The work-around is to do the following:

  • Have a dual core configuration with the same line rate which fits in the next smallest part (xc6slx25t),
  • Or
  • Have a dual core configuration with different line rate which would have to fit in the next smallest part (xc6slx45t)

For LogiCORE CPRI - Release Notes and Known Issues, see (Xilinx Answer 36969)

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
36969 LogiCORE IP CPRI - Release Notes and Known Issues N/A N/A
AR# 40946
Date Created 02/28/2011
Last Updated 11/11/2016
Status Active
Type Known Issues
IP
  • CPRI