I have heard that Xilinx recommends constraining a design fully in a custom UCF file as opposed to using the UCF file generated by Synplify.
What is the reason for this recommendation?
This is a valid question. There is nothing wrong with using the UCF file created by Synplify as long as it covers every path in the design and the constraints are accurate. Generally, most customers over-constraint the synthesis tool to get better performance, but then these constraints are not valid or realistic for implementation.
There is also the issue that the constraintsare created for Synplify, but optimizations (name changes etc.) happen during Synthesis, so these constraints might not cover the full design or be valid when moved into the implementation tools. Also, they might not cover cores and other blocks added to the design after synthesis. Additionally, some of the constraints are not valid for Synthesis tools, although the tool does propagate these to the UCF file. You just need to be careful when using the UCF from synthesis.
There is a general guideline that customers should create a specific UCF file for the implementation tools. This UCF should have constraints that cover the full design, including cores. You should have OFFSET IN, PERIOD and OFFSET OUT as a minimum, plus any associated multi-cycle constraints or TIGs. The PERIOD constraint should allow for input clock jitter. Please see UG612 and the constraints guide for more information on constraints.