We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 41018

7 Series MIG DDR3 SDRAM - How is the PHY Command (mc_cmd) used in conjunction with the ddr command signals (mc_ras, mc_cas, etc)?


The 7 Series MIG DDR3 SDRAM Controller to PHY interface includes a PHY Command bus (mc_cmd) as well as the DDR3 command signals (mc_ras, mc_cas, mc_we, etc). Why are two command interfaces included and how are they used within the PHY?


The 7 Series DDR3 SDRAM MIG PHY includes the PHY Control block which acts as the main control block within the PHY. It controls the flow of addresses, commands, and data between the IN/OUT_FIFOs and ISERDES/OSERDES, and control of the PHASER_IN and PHASER_OUT blocks. The calibration logic (during calibration) or the memory controller (during normal operation) sends PHY Control Words to the PHY Control block while loading commands and data (for write commands) into the IN/OUT_FIFOs. The PHY Control Words define a set of actions the block will complete to execute a DDR3 SDRAM command.

A field within the PHY Control Word is PHY Command. The PHY operates in sequences offour commands. The PHY Command field is set based on whether the sequence of four commands has write, read, or non-data. The PHY Control then reads the address/command and data (for writes) OUT_FIFOs and transfers the associated data to the appropriate IOIs. The memory controller "mc_cmd" signal drives the PHY Command during normal opertion.

The mc_ras/_cas/_we/ signals are what get stored in the address/command OUT_FIFOs by the memory controller of which the PHY Control block determines when to transfer to the IOIs, signifying whether the signals are asserted for the command being processed (i.e., write, read, activate, etc).

Each of these signals is 4-bits because the address/command signals must have values forfour memory clock cycles (each PHY_Clk cycle entailsfour memory clock cycles).

Additional Information

- Refer to the PHY section within ug586_7Series_MIG (DDR3 SDRAM Memory Interface Solution > Core Architecture > PHY).

AR# 41018
Date 12/15/2012
Status Active
Type General Article
  • Virtex-7
  • Kintex-7
  • MIG
Page Bookmarked