When using the x8 Gen 2 128-bit AXI Streaminginterface, it is possible that some packets presented by the user on the transmit interface may be lost.
This problem only affects single cycle packets meaning that the entire TLP is transmitted on one clock cycle on the 128-bit interface. Also, it will only occur if there is an incoming configuration transaction at the same time the packet is presented. Xilinx is currently investigating this issue and this answer record will be updated once a workaround is available.
This issue does not affectthe 64-bit AXI interface or the legacy 128-bit TRN interface.
Revision History 01/18/2012 - Updated; added reference to 45723 03/03/2011 - Initial Release
Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.