AR# 41054


MIG 7 Series DDR3/DDR2 - How does the memory controller send a Read/Write with Auto-Precharge request to the PHY?


How does theMIG 7 Series DDR3 controller send a Read/Write with Auto-Precharge request to the PHY?

Note: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


To request a Write/Read with Auto-Precharge the memory controller sets the PHY Command field of the PHY Control Word (using the mc_cmd signal) to either Write or Read while sending the appropriate command signals and address signals with bit A10 set to 1 (for the auto-precharge) to the command/address OUT_FIFO(s).

Additional Information
For more detailed information on the MIG7 Series DDR3/DDR2 PHY, please see the PHY section withinthe 7 Series FPGA Memory Interface Solutions User Guide(DDR3 SDRAM Memory Interface Solution > Core Architecture > PHY).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
41169 MIG 7 Series Solution Center - Design Assistant - DDR3 SDRAM - Calculating Efficiency and Effective Bandwidth N/A N/A
AR# 41054
Date 09/20/2012
Status Active
Type Solution Center
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