UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 41099

Design Advisory for Virtex-6 FPGA - Synchronous FIFOs must have reset synchronized to RDCLK/WRCLK

Description


When using the Built-In FIFO as a Synchronous FIFO (EN_SYN=TRUE) with asynchronous reset, correct behavior of the FIFO status flags cannot be guaranteed after the first write.

All configurations with EN_SYN=FALSE are not affected by this issue.

Solution


There are two methods to work around this issue:

1. Synchronize the negative edge of reset to RDCLK/WRCLK
2. Set EN_SYN = FALSE

Work-around 1 (*Update for users of 13.1 and previous versions of ISE Design Suite):

Fully synchronize or synchronize only the negative edge (de-assertion) of the reset signal to the FIFO RDCLK/WRCLK.

In ISE Design Suite 13.2 and later versions of software, the reset path is analyzed correctly by the timing tools. There are no additional requirements for Work-around 1 for designs with timing analyzed in ISE Design Suite 13.2 or later.

*In ISE Design Suite 13.1 or previous with the patches provided in (Xilinx Answer 42444), the reset path is analyzed correctly by the timing tools. There are no additional requirements for Work-around 1 for designs with timing analyzed in ISE Design Suite 13.1 or previous with the patches provided in (Xilinx Answer 42444). These designs do not require the constraints described in the following section of Work-around 1.

For ISE Design Suite 13.1 and previous versions of software that do not use the patches provided in (Xilinx Answer 42444), the FIFO reset signal delay must be constrained as follows:

-1: 150 ps < usr_sync_rst < (Tclkper - 768 ps)
-2: 150 ps < usr_sync_rst < (Tclkper - 684 ps)
-3: 150 ps < usr_sync_rst < (Tclkper - 612 ps)

Where 'usr_sync_rst' is the path between the reset synchronizer flop and the FIFO, and 'Tclkper' is the clock period of the FIFO RDCLK/WRCLK.

Example:

For a XC6VLX240T-1FF1156 device, with FIFO RDCLK/WRCLK frequency = 200 MHz and period of 5 ns, the reset can be constrain as follows:

NET "usr_sync_rst" TPTHRU = "constrained_rst";
TIMESPEC TS_tpthru_rst = FROM FFS THRU constrained_rst TO RAMS 4.232 ns;

Check timing analysis to ensure that:
- no timing failures occurred
- none of the reset path delays are 150 ps or smaller



Work-around 2:

Xilinx recommends that designs with the synchronous FIFO with EN_SYN = TRUE use Work-around 1 because it has the least impact on design functionality.

If the timing specified in Work-around 1 is unable to be met, use Work-around 2 which is to change the EN_SYN setting to FALSE. There are many functional and timing differences between the EN_SYN = TRUE and EN_SYN = FALSE settings. Following are the main differences. Please review Chapter 2 of the Virtex-6 FPGA Memory Resources User Guide for full details on the EN_SYN = FALSE, or Dual-clock FIFO behavior.

Main differences when changing to EN_SYN = FALSE:
  • There can be multiple cycles of latency on the assertion/de-assertion of the FIFO flags, and there is one additional cycle of uncertainty on the falling edges of the FIFO flags.
  • The ALMOST_FULL and ALMOST_EMPTY ranges are different. See the tables below for flag latency and range information.
  • Ports REGCE and RSTREG, and DO_REG=0 are not supported when EN_SYN = FALSE. This results in a slight timing difference in the DO clk-to-out which is shown in the Figure labeled 2-1 below.






Revision History:

07/07/2011 - Updated for timing improvements included in patches from Answer Record 42444
07/05/2011 - Updated for timing improvements in ISE Design Suite 13.2
04/11/2011 - Initial Release
AR# 41099
Date Created 03/21/2011
Last Updated 07/08/2011
Status Active
Type Design Advisory
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Less